Senior ASIC Physical Design Engineering Technical Lead

Job Title

Senior ASIC Physical Design Engineering Technical Lead

Role Summary

Lead technical delivery for ASIC physical-design execution on advanced-node chip projects. Responsible for full-chip floorplanning, hierarchical implementation, RTL-to-GDSII flows, timing and power closure, and coordinating signoff methodologies with foundries and IP vendors.

Work as a cross-functional technical lead interfacing with architecture, RTL, DFT, package, EDA vendors, and validation teams to optimize performance, power, and die area.

Experience Level

Senior — expects substantial senior-level physical-design experience consistent with leading full-chip implementation on advanced process nodes (senior technical leadership on tapeouts and flow definition).

Responsibilities

Deliver and lead physical design activities across the full implementation flow and improve design/tool methodologies.

• Create full-chip floorplans based on architecture, foundry guidelines, and IP placement constraints.
• Collaborate with system and package design teams to incorporate requirements into the floorplan.
• Execute hierarchical implementation: partitioning, pin assignment, bump planning, clock planning.
• Perform RTL-to-GDSII implementation: floorplan, power-grid planning, place-and-route, static timing analysis, power integrity, physical verification, and equivalence checks.
• Design and optimize full-chip clock structures, including clock mesh and Flex-HTree methods.
• Apply low-power design methodologies (UPF) across implementation flows.
• Define signoff methodologies with foundry and standard-cell/IP vendors and validate adjustments using post-silicon feedback.
• Analyze existing tool flows and implement incremental or transformative flow improvements; collaborate with EDA vendors and internal tool/flow teams.
• Leverage scripting and AI tools to improve productivity and automation.

Requirements

Must-have technical skills and experience for immediate contribution.

• Must-have: Demonstrated experience with RTL-to-GDSII flow and tapeouts in advanced process technologies (7nm/5nm/3nm or below).
• Must-have: Hands-on experience with full-chip clock mesh and Flex-HTree techniques.
• Must-have: Practical experience with EDA implementation and signoff tools such as Innovus, Tempus/PrimeTime, Redhawk/Voltus, Calibre/Pegasus (or equivalents).
• Must-have: Proficiency in low-power design methodologies and UPF usage for power intent.
• Must-have: Experience in floorplanning, power-grid planning, partitioning, pin-assignment, timing closure, and power-integrity analysis.
• Must-have: Experience working with foundry and standard-cell/IP vendors to define and validate signoff flows.
• Nice-to-have: Strong Python scripting skills and experience using AI tools to improve productivity, including prompt-driven workflows.
• Nice-to-have: Experience with hierarchical design flows, static timing analysis practices (constraints, corners), and post-silicon validation feedback loops.

Education Requirements

Bachelor's degree in Electrical Engineering with ~12+ years of physical-design experience; OR Master's degree in Electrical Engineering with ~8+ years; OR PhD in Electrical Engineering with ~5+ years of physical-design experience. (Source specifies Electrical Engineering degrees with the listed years for this role.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).