Senior ASIC Physical Design Engineering Technical Lead
Cisco SystemsJob Title
Senior ASIC Physical Design Engineering Technical Lead
Role Summary
Lead full-chip physical design for high-performance ASICs within the Common Hardware Group, owning floorplan, implementation flow, timing and power closure, and signoff methodology. Work across RTL, package, DFT, validation, and EDA vendors to optimize performance, power, and die size for advanced process nodes.
Application window expected to close on 2026-08-01.
Experience Level
Senior. See Education Requirements for degree-linked years of physical-design experience (examples: PhD +5, MS +8, BS +12).
Responsibilities
The role focuses on full-chip implementation, methodology improvements, and cross-team coordination.
- Create full-chip floorplans based on architecture, foundry guidelines, and IP placement constraints.
- Collaborate with system and package teams to translate requirements into the floorplan.
- Perform hierarchical implementation: partitioning, pin assignment, clock planning, and bump planning.
- Lead RTL-to-GDSII flow: floorplan, power-grid planning, place-and-route, static timing analysis, power integrity, physical verification, and equivalence checks.
- Optimize designs for performance, power, and die size; apply low-power methodologies (UPF).
- Define and validate signoff methodologies with foundry and IP vendors and adjust based on post-silicon feedback.
- Analyze existing tool flows, identify gaps, and implement incremental or transformative enhancements; coordinate with EDA vendors and tool teams.
Requirements
Must-have technical skills and demonstrated experience in advanced physical design.
- Hands-on RTL-to-GDSII/tapeout experience at advanced nodes (7nm/5nm/3nm or below).
- Experience with EDA tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus, Calibre, Pegasus, or equivalents.
- Expertise in full-chip clock strategies (clock mesh, H-tree) and static timing analysis, constraints, and closure.
- Experience with power-grid planning, power integrity analysis, and low-power design practices.
- Proven ability to collaborate with RTL, DFT, implementation, validation, packaging, and EDA vendor teams.
- Track record of improving tool flows and implementation methodologies.
- Preferred: experience with Python and using AI tools to improve productivity.
Education Requirements
Bachelor’s Degree in Electrical Engineering with 12+ years of physical design experience; or Master’s Degree in Electrical Engineering with 8+ years of physical design experience; or PhD in Electrical Engineering with 5+ years of physical design experience. (These degree-and-experience combinations were specified by the employer.)
About the Company
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).
