Senior ASIC Physical Design Engineering Technical Lead

Job Title

Senior ASIC Physical Design Engineering Technical Lead

Role Summary

Lead physical implementation for full-chip ASIC designs with responsibility for floorplanning, clocking, power-grid planning, place-and-route, timing closure, power integrity and signoff methodologies. Work on advanced process nodes and coordinate with RTL, DFT, system/package teams, EDA vendors and foundries to meet performance, power and die-size goals.

Experience Level

Senior-level. Requires extensive senior ASIC physical design experience in advanced-node tapeouts.

Responsibilities

Deliver and improve physical design flows and lead chip-level implementation activities.

• Create full-chip floorplans considering architecture, IP placement and foundry constraints.
• Collaborate with system and package design teams to incorporate system requirements into the floorplan.
• Perform hierarchical implementation tasks: partitioning, pin assignment, clock planning and bump planning.
• Implement RTL-to-GDSII flow: floorplan, power grid design, place-and-route, static timing analysis, power integrity and physical verification.
• Optimize designs for performance, power and die size; define signoff methodologies with foundry and IP vendors and iterate from post-silicon feedback.
• Analyze and improve tool flows and methodologies; work with RTL, DFT, EDA vendors and tool teams to enable robust flows.
• Apply low-power design techniques and integrate UPF-based flows into implementation.
• Use scripting and productivity tools, including AI-assisted methods, to improve engineering efficiency.

Requirements

Key technical skills and domain experience required for the role. See Education Requirements for degree and years details.

• Extensive hands-on experience with RTL-to-GDSII flow and tapeouts at advanced process nodes (7nm/5nm/3nm or below).
• Proven experience with chip-level floorplanning, partitioning, pin-assignment and power-grid planning.
• Strong STA skills: defining constraints, timing exceptions, corners and closure techniques.
• Experience with EDA implementation and verification tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus, Calibre/Pegasus.
• Experience implementing chip-level clock topologies (H-Tree or mesh) and custom clock methods.
• Familiarity with power integrity analysis and physical verification flows.
• Experience scripting in Python for automation and flow integration.
• Ability to work cross-functionally with foundry, IP providers, EDA vendors and post-silicon teams.
• Nice-to-have: practical experience using AI tools to boost productivity and validating signoff flows against post-silicon results.

Education Requirements

Bachelor's degree in Electrical Engineering (or equivalent) with 12+ years of physical design experience; or Master's degree in Electrical Engineering with 8+ years; or PhD in Electrical Engineering with 5+ years. The role expects education in Electrical Engineering or a closely related technical field.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).