Senior ASIC Physical Design Engineer (with Security Clearance)

Job Title

Senior ASIC Physical Design Engineer (with Security Clearance)

Role Summary

Senior engineer responsible for digital back-end physical design and verification of custom ASICs in the Miniature Device Technologies Group at the Johns Hopkins APL. The role covers synthesis through a completed, verified top-level layout ready for tapeout and supports mixed-signal and low-power miniature systems for national security applications.

Experience Level

Senior — requires 6+ years of back-end ASIC design experience.

Responsibilities

Lead and execute digital back-end physical design tasks and support cross-disciplinary integration to deliver tapeout-ready ASICs.

• Implement digital back-end flow from synthesis to completed, verified top-level layout for tapeout.
• Floorplan top-level layout for digital and mixed-signal ASICs; perform design partitioning to meet timing.
• Perform static timing analysis and timing closure activities.
• Insert SCAN and BIST for test coverage and support testability strategies.
• Execute physical verification including DRC, MCD, and LVS checks.
• Debug and resolve back-end issues at RTL and gate-level in collaboration with digital designers.
• Perform custom physical layout and top-level custom modifications as needed.
• Contribute to process selection and ASIC technology assessment for new designs.
• Support tooling/environment improvements and scripting for the ASIC design flow.
• Provide guidance and mentorship to junior physical design engineers and work with cross-functional teams to meet project goals.

Requirements

Must-have qualifications and clearances.

• Minimum 6 years of experience specifically performing back-end ASIC physical design.
• Proven proficiency with Cadence tools for back-end flow implementation.
• Proven proficiency with Siemens Calibre for physical verification.
• Experience with timing analysis, floorplanning, SCAN/BIST insertion, and tapeout readiness.
• U.S. citizenship and ability to obtain an Interim Secret clearance by start date and ultimately a Secret clearance.
• Ability to perform DRC, MCD, and LVS physical verification and debug related issues.
• Strong collaboration, problem-solving skills, and ability to lead technical tasks.

Nice-to-have:

• Experience with custom physical layout in Cadence Virtuoso.
• Experience with Siemens ASIC design tools for back-end flow implementation.
• Extensive experience in ASIC technology characterization for process selection.
• Active security clearance or prior single-scope background investigation.
• Experience scripting or enhancing ASIC design environments and EDA flows.

Education Requirements

Possess an Associate's degree in a technical field, or an equivalent combination of education, certifications, and practical experience. The posting explicitly allows equivalent practical experience in lieu of the degree.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.