Senior ASIC Physical Design Engineer (security clearance required)

Job Title

Senior ASIC Physical Design Engineer (security clearance required)

Role Summary

Senior physical design engineer responsible for digital back-end flow and top-level layout for miniature, low-power ASICs used in national security applications. You will work in the Miniature Device Technologies Group and collaborate with digital design, verification, and software teams to deliver verified, tapeout-ready ASICs.

Experience Level

Senior — requires approximately 6+ years of back-end ASIC physical design experience (specified minimum: 6 years).

Responsibilities

Primary duties focus on digital back-end implementation, verification, and integration with front-end design.

• Lead digital back-end flow from synthesis through a completed, verified top-level layout ready for tapeout.
• Create top-level floorplans for digital and mixed-signal ASICs and perform design partitioning to meet timing.
• Perform timing analysis and work with designers to debug RTL and gate-level timing issues.
• Insert SCAN and BIST to maximize defect coverage and support testability.
• Execute physical verification checks including DRC, LVS, and MCD using industry tools.
• Perform custom physical layout and make top-level modifications as required.
• Evaluate process options for new designs, assessing size, power, IP availability, and manufacturability.
• Contribute to scripting and environment enhancements to improve ASIC design flows.
• Mentor junior physical design engineers and collaborate across disciplines to meet project objectives.

Requirements

Must-have technical skills, clearance eligibility, and experience for successful performance in this role.

• Proven experience with Cadence ASIC back-end design tools for synthesis, place-and-route, and signoff flows.
• Proficiency with Siemens Calibre for physical verification (DRC/LVS/MCDC).
• Minimum of 6 years performing back-end ASIC physical design.
• Ability to obtain an Interim Secret clearance by start date and ultimately obtain Secret; position requires eligibility for a government security clearance.
• U.S. citizenship required for clearance eligibility.
• Strong troubleshooting skills in RTL and gate-level contexts; familiarity with mixed-signal integration is beneficial.
• Nice-to-have: experience with Cadence Virtuoso custom layout, Siemens ASIC back-end toolset experience, ASIC technology characterization for process selection, or an active security clearance.

Education Requirements

Associate's degree in a technical field, or an equivalent combination of experience, education, and/or certifications. The posting explicitly allows equivalent practical experience in place of the degree.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.