Senior ASIC Physical Design Engineer (requires security clearance)

Job Title

Senior ASIC Physical Design Engineer (requires security clearance)

Role Summary

Join the Miniature Device Technologies Group to lead digital back-end physical design for custom ASICs used in miniature, low-power systems for national security missions. Work with digital designers, verification, software, and cross-functional teams to deliver validated, tapeout-ready top-level layouts.

Experience Level

Senior — typically requires 6+ years of hands-on back-end ASIC physical design experience.

Responsibilities

The role owns digital back-end flow and top-level physical implementation from synthesis through final verification and tapeout.

• Implement digital back-end flow: synthesis, placement, routing, and completion of a verified top-level layout ready for tapeout.
• Floorplan top-level digital and mixed-signal ASIC layouts and perform design partitioning to meet timing goals.
• Perform timing analysis, STA, and debug RTL/gate-level issues with digital designers.
• Insert SCAN and BIST to maximize defect coverage.
• Execute physical verification (DRC, MCD, LVS) and sign-off checks.
• Create and modify custom physical layouts and perform top-level custom fixes as needed.
• Support process selection and ASIC technology characterization for proposals and new designs.
• Develop and maintain scripts and environment improvements for ASIC design flows.
• Provide technical leadership and mentor junior physical design engineers; collaborate across teams to meet project goals.

Requirements

Key technical and security requirements for consideration.

• Must have demonstrated experience with Cadence ASIC back-end tools for implementing back-end flows.
• Must have experience using Siemens Calibre (physical verification) tools.
• Minimum of 6 years performing back-end ASIC physical design.
• Ability to obtain an Interim Secret security clearance by start date and ultimately obtain Secret clearance; eligibility requires U.S. citizenship.

Nice-to-have:

• Experience with custom physical layout in Cadence Virtuoso.
• Experience using Siemens back-end ASIC implementation tools.
• Extensive experience in ASIC technology characterization and process selection.
• Active security clearance or prior single-scope background investigation.

Education Requirements

Associate's degree in a technical field, or equivalent combination of education, certifications, and practical experience is acceptable. The posting explicitly allows equivalent level experience/education/certifications in lieu of a degree.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.