Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

The engineer will execute block- and chip-level physical design for large SoC projects, taking designs from RTL to GDSII and preparing databases for manufacturing and tapeout. This role works on floorplanning, P&R, CTS, sign-off verification and integration of IPs and sub-chips in collaboration with architecture, frontend, DV, packaging and DFT teams.

Experience Level

Senior — typically candidates have multiple years of physical design experience; the posting indicates expectations equivalent to 3+ years with a BS or 2+ years with an MS in a relevant field.

Responsibilities

Primary responsibilities include block-level physical design, integration, verification and collaboration across teams to achieve successful tapeouts.

• Implement physical design at large SoC block level from RTL to GDSII and prepare design database for manufacturing.
• Integrate blocks, IPs and sub-chips; coordinate with IP vendors on integration requirements.
• Work with the packaging team on Microbump/Probe Bump/Bump/Pad placement and packaging-related planning.
• Build block-level floorplans: block pins, macro placement/alignment, power grid and related constraints.
• Develop block-level clock networks and clock structure in collaboration with clock experts; generate static timing constraints.
• Analyze and optimize feedthroughs and repeater insertion between blocks; perform place-and-route to meet timing, area and power goals.
• Generate and apply ECOs to address timing, SI, EM/IR, PV and formal verification issues.
• Integrate DFT considerations into physical design and run physical verification flows (LVS/DRC/ERC/ANT), addressing violations.
• Collaborate with architecture, RTL/frontend, DV and packaging teams to ensure cohesive implementation and successful tapeouts.

Requirements

Must-have technical skills and experience required for the role; a few preferred items are noted separately.

• Deep experience in large SoC physical design and IP integration (block- and chip-level).
• Strong knowledge of physical design flows and practices: synthesis, floorplanning, place & route, CTS, repeater/feedthrough strategies.
• Experience implementing block-level power grids and clock networks.
• Proven ability to debug and resolve LVS/DRC/ERC/ANT and other physical verification issues.
• Familiarity with HDL (e.g., Verilog) for timing fixes and integration troubleshooting.
• Proficiency scripting in Linux environments (Perl, TCL, Python) to automate flows and analyses.
• Real chip tapeout experience at advanced nodes (7 nm or below) with successful signoff and delivery history.
• Strong problem-solving, debugging skills and ability to work in cross-functional teams.
• Nice-to-have: exposure to 2.5D/3D packaging, DFT, and custom place-and-route experience.

Education Requirements

BS in Electrical Engineering, Computer Engineering or related field with 3+ years of block/full-chip physical design experience; OR MS in a related field with 2+ years of related experience. (Degrees are listed in the original posting as the primary academic requirements.)

About the Company

Company: Hewlett Packard Enterprise

Headquarters: Spring, TX, United States

Global enterprise technology company delivering hybrid cloud, edge-to-cloud platforms, servers, storage, networking, and IT services to help organizations build, run, and secure applications and infrastructure at scale.