Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Work in the Miniature Device Technologies Group at Johns Hopkins APL to develop ultra-small, low-power ASIC solutions for national security applications. The role leads digital back-end physical design and collaborates with digital, verification, and software teams to deliver tapeout-ready layouts.

Experience Level

Senior-level — typically requires about 6 years of back-end ASIC physical design experience and responsibility for technical leadership and mentoring.

Responsibilities

The role covers end-to-end digital back-end physical design and verification tasks.

• Implement digital back-end flow from synthesis through top-level floorplanning to a verified, tapeout-ready layout.
• Perform timing analysis, partitioning, and timing closure.
• Insert SCAN and BIST to maximize test coverage.
• Run physical verification (DRC, MCD, LVS) and resolve violations.
• Perform or oversee custom physical layout and top-level custom modifications as needed.
• Evaluate process selection and technology characterization for size, power, and IP availability.
• Debug back-end related RTL and gate-level issues in collaboration with digital designers.
• Develop scripts and environment enhancements to improve the ASIC design flow.
• Provide technical leadership and mentor junior physical design engineers.

Requirements

Must-have skills, security requirements, and relevant experience.

• Minimum 6 years of hands-on back-end ASIC physical design experience.
• Proficient with Cadence back-end design tools and flow implementation.
• Proficient with Siemens Calibre for physical verification.
• Eligible to obtain an Interim Secret clearance by start date and a Secret clearance subsequently; U.S. citizenship required.
• Experience with timing analysis, floorplanning, SCAN/BIST insertion, and physical verification.
• Ability to debug and resolve RTL and gate-level physical implementation issues.
• Strong scripting skills and experience improving ASIC design environments.
• Nice-to-have: experience with Cadence Virtuoso custom layout, Siemens ASIC toolset, ASIC process characterization, or an active security clearance.

Education Requirements

Associate's degree in a technical field, or an equivalent combination of education, certifications, and practical experience as explicitly allowed by the posting.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.