Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Lead back-end physical design for miniature and mixed-signal ASICs in the Miniature Device Technologies Group, delivering tapeout-ready top-level layouts and physical verification. Work with digital designers, verification, and software teams to resolve back-end issues and guide technical decisions for process selection, size, and power trade-offs.

This role emphasizes hands-on implementation (synthesis, floorplanning, timing closure, SCAN/BIST, DRC/LVS) and mentoring junior engineers to meet mission-driven requirements.

Experience Level

Senior — requires 6+ years of experience specifically performing back-end ASIC design.

Responsibilities

Primary responsibilities include:

• Own digital back-end flow from synthesis to verified top-level layout ready for tapeout.
• Top-level floorplanning for digital and mixed-signal ASICs.
• Perform timing analysis, partitioning, and timing closure activities.
• Insert SCAN and BIST to maximize defect coverage.
• Execute physical verification (DRC, DRC+, MCD, LVS) and resolve violations.
• Perform custom physical layout and top-level custom modifications as needed.
• Identify and debug back-end related RTL and gate-level issues with digital designers.
• Contribute to environment enhancements and scripting to improve flows.
• Provide technical leadership and mentorship to junior physical design engineers.
• Collaborate with cross-functional teams to meet project goals and drive process improvements.

Requirements

Minimum qualifications and required skills:

Must-have:

• 6+ years of hands-on back-end ASIC physical design experience.
• Skilled with Cadence back-end tools for synthesis/floorplanning/implementation.
• Skilled with Siemens Calibre for physical verification.
• Proven ability to perform timing analysis, partitioning, SCAN/BIST insertion, and debug RTL/gate-level back-end issues.
• Ability to obtain an Interim Secret security clearance by start date and ultimately a Secret clearance; U.S. citizenship required for clearance eligibility.

Nice-to-have:

• Experience with custom physical layout in Cadence Virtuoso.
• Experience with Siemens ASIC implementation tools.
• Extensive knowledge of ASIC technology characterization and process selection trade-offs (size, power, IP availability).
• Active security clearance or prior single-scope background investigation.

Education Requirements

Associate's degree in a technical field, or an equivalent combination of education, experience, and/or certifications.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.