Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

The Senior ASIC Physical Design Engineer will lead digital back-end physical design activities for compact, low-power ASICs used in mission-critical systems. The role sits within a miniature device technologies team that integrates ASIC, PCB, FPGA, embedded software, and signal processing to deliver specialized hardware for national security applications.

Experience Level

Senior — requires at least 6+ years of specific back-end ASIC physical design experience.

Responsibilities

Deliver complete digital back-end flows and top-level layouts through tapeout and support cross-functional design integration and verification.

• Drive digital back-end flow from synthesis, floorplanning, and timing closure to final top-level layout.
• Perform timing analysis, design partitioning, and timing closure activities.
• Insert SCAN and BIST for improved test coverage and oversee testability strategies.
• Execute physical verification including DRC, MCD, LVS and other foundry checks.
• Perform custom physical layout and top-level fixes as required.
• Work with RTL and gate-level designers to identify and resolve back-end issues.
• Support process selection and technology characterization for new proposals and designs.
• Contribute to ASIC design environment improvements and scripting as needed.
• Provide technical leadership and mentorship to junior physical design engineers.
• Coordinate with verification, digital design, and software teams to meet project goals.

Requirements

Must-have technical skills, security eligibility, and experience for this position.

• Proven experience with Cadence ASIC back-end design tools and flows.
• Experience using Siemens Calibre or equivalent physical verification tools for DRC/LVS/MCD.
• 6+ years of hands-on back-end ASIC physical design experience.
• Ability to obtain an Interim Secret security clearance by start and ultimately a Secret clearance; U.S. citizenship required.

Nice-to-have:

• Experience with custom physical layout in Cadence Virtuoso.
• Familiarity with Siemens ASIC implementation tools for back-end flows.
• Experience in ASIC technology characterization and process selection.
• Active security clearance or prior single-scope background investigation.

Education Requirements

Associate's degree in a technical field is listed as the baseline, or an equivalent combination of education, certifications, and practical experience.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.