Senior ASIC Implementation Engineer, Low Power AI
QualcommJob Title
Senior ASIC Implementation Engineer, Low Power AI
Role Summary
Join the ASICS Engineering team working on ultra-low power AI subsystems for audio and context-aware applications. The role focuses on ASIC implementation tasks for a low-power SoC block that integrates always-on IPs and multiple power domains.
Initial technical focus includes power-intent validation and power optimization while contributing to synthesis, timing, ECOs, STA, CDC validation, and implementation flows.
Experience Level
Senior. The posting lists minimum experience expectations (see Education Requirements), and the role requires professional ASIC implementation experience and hands-on tool usage.
Responsibilities
Primary implementation and power-optimization duties; specific tasks depend on project needs.
- Perform logic synthesis and related flow tasks.
- Define and validate timing constraints; run static timing analysis (STA).
- Implement ECOs and perform design linting and CDC validation.
- Power-intent validation (CLP/UPF) and power analysis/optimization.
- Model and analyze performance, area, power, and cost trade-offs for micro-architectures.
- Contribute to implementation methodologies and flows.
- Occasionally perform RTL development or other ASIC design tasks as needed.
- Initial focused tasks: CLP (RTL/netlist), PTPX / power pro, and power analysis/optimization.
Requirements
Must-have technical skills and experience for immediate contribution.
- 2+ years of professional ASIC hardware design and/or implementation experience.
- Proficient in Verilog and/or VHDL with the ability to write synthesizable, readable RTL.
- Strong understanding of ASIC/VLSI design concepts.
- Experience with logic synthesis using Synopsys and/or Cadence toolchains.
- Experience with STA and timing constraint methodology.
- Experience with CDC techniques and validation.
- Detail-oriented with strong analytical and debugging skills.
Nice-to-have:
- Working knowledge of the UPF specification and power-intent flows.
- Experience in high-speed/low-power ASIC design in a Unix environment.
- Familiarity with clock-domain crossing tools and techniques.
- Scripting skills (Python, Perl, Tcl, or C).
- Strong written and verbal communication and collaboration skills.
Education Requirements
Required: Bachelor's degree in Science, Engineering, or related field plus 2+ years of ASIC design/verification experience; OR Master's degree in Science, Engineering, or related field plus 1+ year of ASIC design/verification experience; OR PhD in Science, Engineering, or related field. Fields cited include science and engineering or related technical disciplines.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
