Senior ASIC & FPGA Design Engineer

Job Title

Senior ASIC & FPGA Design Engineer

Role Summary

The Senior ASIC & FPGA Design Engineer will lead the Command Launch Assembly (CLA) FPGA team within Missiles & Fire Control (MFC) to develop reliable FPGA hardware for the Next Generation Short Range Interceptor (NGSRI).

This role oversees the FPGA lifecycle from architecture through documentation, coordinates with cross-functional teams (systems, software, hardware, mechanical, test, manufacturing, quality), and mentors junior engineers.

Experience Level

Senior — minimum 3 years of FPGA design and verification experience.

Responsibilities

Primary responsibilities include FPGA architecture, RTL implementation, verification, board-level debug, and delivering production-ready design packages compliant with aerospace standards.

• Define FPGA architecture and produce detailed design specifications.
• Implement RTL in VHDL, Verilog, or SystemVerilog to meet performance, power, and reliability targets.
• Develop synthesis, place-and-route, and timing-closure strategies for target FPGA families.
• Build test plans, simulation models, and verification environments (UVM, SystemC, Python).
• Lead hardware-in-the-loop tests, board-level debugging, and subsystem integration.
• Translate system-level performance, safety, and reliability requirements into FPGA architectures.
• Perform timing analysis, power budgeting, and device selection optimization.
• Manage configuration control with GitLab and ensure traceability of design artifacts.
• Produce complete design packages that meet aerospace and company standards and support program schedules.
• Mentor junior engineers and promote best practices in FPGA development.

Requirements

Must-have technical skills, security eligibility, and hands-on experience needed to perform the role.

• Minimum 3 years of FPGA design and simulation/verification experience.
• Proficiency in HDL: VHDL, Verilog, SystemVerilog.
• Experience with Xilinx/AMD toolsets (Vivado, Vitis) and UltraScale design methodology.
• Familiarity with FPGA simulation tools (e.g., Synopsys VCS) and Synopsys EDA tool suite.
• Strong understanding of digital design principles including timing analysis and signal integrity.
• Experience with high-speed interfaces (AXI, Ethernet, TCP/IP, PCIe).
• Practical lab debug experience with high-speed test equipment and board-level troubleshooting.
• Experience with configuration control systems (GitLab preferred) and delivering audited design packages.
• Experience in full ASIC/FPGA lifecycle from architecture through validation.
• U.S. Citizenship and ability to obtain a DoD Secret clearance.

Nice-to-have:

• Experience with C/C++, MATLAB/Simulink, SystemC, UVM, Simulink/HDL Coder integration.
• Familiarity with MicroSemi/Microchip and other FPGA families, Synopsys Synplify, NCSim, ChipScope.
• Knowledge of cryptographic algorithms (e.g., AES) and networking/debugging tools (tcpdump, Wireshark).

Education Requirements

Bachelor's degree in Electrical Engineering or a related STEM field is required; a Master's degree is preferred.

About the Company

Company: Lockheed Martin

Headquarters: Bethesda, Maryland, United States

Lockheed Martin is a global aerospace and defense company that specializes in the development of innovative technologies for national security, aerospace, and space exploration. With a commitment to harnessing the potential of space, Lockheed Martin aims to cultivate innovation, reduce costs, and advance holistic solutions across military and civilian sectors, focusing on future-ready technologies.