Senior ASIC DFT Engineer

Job Title

Senior ASIC DFT Engineer

Role Summary

Responsible for defining and implementing design-for-test (DFT) architectures and flows for advanced SoC/ASIC designs, and for supporting post-silicon bring-up and production test. The role spans pre-silicon DFT insertion, ATPG and MBIST pattern generation, gate-level validation, and converting patterns for ATE deployment.

Works with design, product, and test-engineering teams to ensure testability, reduce test time, and improve manufacturing yield.

Experience Level

Senior - requires 3+ years of hands-on DFT experience in advanced SoC/ASIC development.

Responsibilities

Primary technical responsibilities across pre-silicon and post-silicon phases.

• Define and implement comprehensive DFT architectures (scan, ATPG, MBIST, JTAG including IEEE 1149.1/1500/1687).
• Perform scan-chain insertion, stitching, and optimization for timing and power grid compatibility.
• Integrate MBIST controllers, repair mechanisms, and custom memory test routines.
• Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware) and perform fault grading.
• Run Verilog/SystemVerilog gate-level simulations and SDF-annotated validation for DFT features and vector cleanliness.
• Perform DFT linting and rule checking with industry tools; resolve DFT tool issues and violations.
• Convert ATPG/MBIST patterns to tester formats (e.g., STIL/WGL) for ATE deployment and production testing.
• Support post-silicon bring-up: debug DFT features, debug silicon failures, and iterate on test patterns.
• Collaborate with Product and Test Engineering to optimize test time and improve yield.

Requirements

Must-have technical skills and domain experience; preferred items listed separately.

• 3+ years hands-on DFT experience in advanced SoC/ASIC designs.
• Proficiency in Verilog and SystemVerilog for DFT integration and wrapper creation.
• Practical experience with scan insertion, compressed scan architectures (e.g., EDT, SmartTest), and boundary-scan integration.
• Strong ATPG background: generate, debug, and fault-grade Stuck-at, At-Speed, and related test patterns.
• MBIST experience: insertion, MBIST architecture design, and memory repair schemes.
• Understanding of JTAG/TAP controllers and board/chip-level test logic (IEEE 1149.x).
• Direct post-silicon support experience: bringing patterns to silicon and supporting production yield ramp.

Preferred / nice-to-have:

• Scripting for automation (Tcl, Python, or Perl).
• Experience with advanced DFT topics such as high-speed I/O testing, SerDes loopback, or analog DFT.
• Familiarity with synthesis tools (Synopsys Design Compiler, Cadence Genus) and STA constraint creation for DFT modes.

Education Requirements

Not specified.

About the Company

Company: MetAntz

Provider of engineering and technical staffing or consulting services, placing specialized engineers in semiconductor and electronics roles (DFT/ASIC/SoC domains).