Senior ASIC Design Verification Engineer

Job Title

Senior ASIC Design Verification Engineer

Role Summary

Senior engineer on Cisco's Silicon One team responsible for architecting and delivering verification solutions for high-performance ASICs used in switching, routing, and wireless products. The role leads verification efforts across block, cluster, and chip levels and supports lab bring-up and post-silicon validation.

Experience Level

Senior - job expects an experienced engineer. Typical background per posting: Bachelor's degree plus ~7 years relevant experience, or Master's degree plus ~4 years relevant experience (see Education Requirements).

Responsibilities

Accountable for verification architecture, environment development, and execution across block, cluster, and chip levels.

• Define verification architecture and own complex functional blocks through design completion.
• Develop and maintain cluster- and top-level DV environments; build environments from scratch when required.
• Create reusable verification methodologies and infrastructure to support advanced design architectures.
• Develop and execute directed and constraint-random tests; implement and review code and functional coverage.
• Run and qualify RTL via gate-level simulations with timing annotation; support emulation platforms.
• Debug issues across ASIC, software, and system levels; assist with lab bring-up and post-silicon validation.
• Lead or mentor verification team members and coordinate cross-team issue resolution at cluster and chip levels.

Requirements

Must-have technical skills and experience for immediate contribution.

• Strong experience with SystemVerilog and UVM-based verification methodologies and Object-Oriented Programming concepts.
• Proven track record in verification architecture, environment development, and reusable verification code.
• Experience leading verification efforts or managing project assignments across teams.
• Scripting proficiency in Python and/or Perl for testbench automation and infrastructure tasks.
• Ability to perform gate-level simulation qualification and to debug at RTL, netlist, and system levels.

Nice-to-have:

• Experience with forwarding logic, parsers, or P4.
• Familiarity with emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
• Knowledge of formal verification tools (e.g., IEV or VC Formal).
• Domain knowledge in protocols such as PCIe, CXL, Ethernet, RDMA, DDR, or TCP.

Education Requirements

Posting specifies either: Bachelor's degree in Computer, Electrical, or Electronics Engineering with ~7 years of relevant ASIC design/verification experience, OR a Master's degree with ~4 years of relevant ASIC design/verification experience. (Degrees and years were stated in the source.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).