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Senior ASIC Design Engineer – Clocks IP

NVIDIA
August 17, 2026
Full-time
Remote friendly (Santa Clara, California, United States)
Worldwide
$136,000 - $264,500 USD yearly
RTL Design Jobs, Level - Senior

Job Title

Senior ASIC Design Engineer – Clocks IP

Role Summary

Member of the Clocks team responsible for architecting and implementing GPU and CPU on-chip clocking. Work spans micro-architecture, RTL, timing and physical design, verification, and silicon bring-up across multiple internal teams.

Collaborate with front-end architects, physical design, timing, DFT, software, and silicon validation teams to deliver clocking solutions meeting functional, physical, and test requirements.

Experience Level

Senior — 3+ years of relevant work experience (as stated in the posting).

Responsibilities

Design, implement, and deliver clocking RTL and architecture for GPUs, CPUs, and SoCs. Typical responsibilities include:

  • Architect clock domains to meet functional, physical and testing requirements.
  • Design clocking networks and topologies in RTL considering PPA and timing closure.
  • Collaborate with floorplanning and physical implementation teams on clock placement and routing constraints.
  • Work with software teams to define clock programming models and sequences.
  • Provide clock RTL and documentation to verification, timing, and DFT teams.
  • Participate in end-to-end ASIC cycle: micro-architecture, implementation, sign-off, and silicon bring-up and debug.

Requirements

Key technical skills and experience required or strongly preferred.

  • 3+ years of relevant ASIC design experience.
  • Deep understanding of logic optimization techniques and PPA trade-offs.
  • RTL design experience (Verilog); knowledge of verification and logic synthesis.
  • Strong scripting and coding skills (Python or equivalent).
  • Excellent interpersonal skills and ability to collaborate across multiple teams.

Nice-to-have:

  • Experience implementing on-chip clocking networks and clock controllers.
  • Experience with silicon debug, scalable design architectures, and system-level issues like power and noise.
  • Familiarity with physical-level effects (noise, crosstalk, OCV) and high-speed clocking concerns.

Education Requirements

BS in Electrical Engineering or equivalent practical experience required; MS preferred. The posting allows equivalent experience in lieu of degree.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

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Date Posted: 2026-08-17