Senior ASIC Design Engineer

Job Title

Senior ASIC Design Engineer

Role Summary

Design and deliver high-performance, production-quality RTL for custom AI inference silicon. The role owns block-level microarchitecture, RTL implementation, and PPA for assigned IP, works closely with verification and physical design, and supports bring-up and post-silicon debug.

This position is an engineering leadership role that also mentors junior engineers and drives design reviews and best practices.

Experience Level

Senior — requires substantial hands-on ASIC/SoC RTL design experience; posting specifies 8+ years.

Responsibilities

Primary responsibilities include microarchitecture, RTL delivery, integration, and cross-functional signoff.

• Define and document microarchitecture for complex IP blocks and subsystems.
• Deliver production-quality, parameterized SystemVerilog RTL with clear interfaces and embedded assertions.
• Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with physical design on floorplan and timing closure.
• Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets.
• Architect and integrate high-performance interconnects, DMA engines, coherency logic, and high-speed memory interfaces.
• Engage with IP vendors and internal stakeholders to ensure seamless integration.
• Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists.
• Contribute automation flows to improve team efficiency and reproducibility.
• Partner with Verification to define test plans and reference models and correlate models against RTL.
• Support bring-up, post-silicon debug, and customer engagements as required.
• Mentor junior engineers and lead design reviews advocating best-in-class solutions.

Requirements

Must-have technical skills and experience required to perform the role.

• 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon.
• Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness.
• Proven track record leading designs from specification through RTL to signoff with strong PPA results.
• Extensive experience with front-end flows and major EDA tool suites.
• Hands-on experience with high-performance memory interfaces and interconnects (HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI), cache/memory hierarchies, and high-throughput datapaths.
• Strong cross-functional communication and collaboration skills; experience working with verification and physical design teams.

Nice-to-have:

• Experience with DFT, lint, synthesis optimization, and physical-design collaboration.
• Experience building automation flows, reusable IP packaging, and signoff checklists.
• Demonstrated leadership and mentorship within engineering teams.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

About the Company

Company: Positron AI

Positron AI designs custom hardware systems and SoC solutions to accelerate AI inference, focusing on high-performance, energy-efficient alternatives to traditional GPU-based inference platforms.