Senior Architect, Memory Compiler Design

Job Title

Senior Architect, Memory Compiler Design

Role Summary

Lead architecture and delivery of memory compiler IP (SRAM, register files, ROM, TCAM) across circuit design, automation, verification, and signoff. Serve as the technical owner for memory compiler features and PPA tradeoffs, collaborating with product, verification, and customer teams.

The role focuses on transistor-level analog design, compiler flow automation, and mentoring engineers to deliver robust memory IP for advanced process nodes.

Experience Level

Senior — requires extensive experience; the role expects roughly 20+ years of hands-on experience designing embedded memory IP and related compiler flows.

Responsibilities

Key responsibilities include end-to-end architecture, circuit design, automation, verification, and team mentorship for memory compiler products.

• Architect and develop memory compiler IP across SRAM, register file, ROM, and TCAM technologies, owning the full flow from circuit design through verification and signoff.
• Design and optimize analog circuits at the transistor level using Hspice/XA, balancing performance, power, and area for advanced nodes.
• Build and refine compiler flows and automation using Python to generate designs, run verification, and characterize results.
• Drive functional verification and signoff across process corners, voltage ranges, and operating conditions.
• Collaborate with product engineering, verification, and customer support to align features with market and customer requirements.
• Mentor engineers across circuit design, memory architecture, and compiler methodology.
• Contribute to technical roadmaps and architecture decisions that define future memory IP.

Requirements

Must-have technical skills and experience; listed "nice-to-have" items are noted separately.

• Must-have: 20+ years of hands-on experience designing embedded memory IP (SRAM, register files, ROM, TCAM) with deep circuit-level and verification expertise.
• Must-have: Proven experience building or operating memory compiler flows from architecture through automated design generation and signoff.
• Must-have: Strong proficiency in Python for scripting, automation, and flow development.
• Must-have: Expert-level experience with Hspice or XA for analog circuit simulation, optimization, and characterization.
• Must-have: Solid understanding of industry-standard verification tools and signoff flows for memory IP.
• Nice-to-have: Experience with advanced process nodes (7nm and below).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related technical field (explicitly stated).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.