Senior Analog/Mixed-Signal IC Design Engineer - Acacia (Hybrid)

Job Title

Senior Analog/Mixed-Signal IC Design Engineer - Acacia (Hybrid)

Role Summary

Member of the mixed-signal IC design group working on high-speed, high-accuracy analog and mixed-signal circuits for optical transceivers (100G, 400G, 1T) that integrate into ASICs. The role is hybrid with a three-day-per-week on-site cadence at the San Jose, CA office.

Primary mission: architect, design, layout, verify and productize ultra-deep-submicron CMOS analog/mixed-signal blocks for optical communications transceivers and collaborate with DSP, package, system and module teams to meet system-level requirements.

Experience Level

Senior-level. See Education Requirements for degree-based experience equivalencies; typical hires will have multiple years of senior-level IC design and leadership experience.

Responsibilities

Core responsibilities include leading complex analog/mixed-signal blocks from concept through production and coordinating across engineering disciplines.

• Architect, design, layout, measure and productize ultra-deep-submicron CMOS analog/mixed-signal ICs.
• Lead a large block on complex chips, mentor engineers, track deliverables and perform peer reviews.
• Develop high-speed AMS circuits (serial links, data converters, PLLs, equalizers, etc.) and ensure performance targets are met.
• Collaborate with packaging and hardware teams to meet signal and power integrity requirements.
• Define and apply robust design methodology for tape-out, bring-up, test and manufacturability.

Requirements

Must-have technical skills and experience. Degree-based experience equivalencies are summarized in Education Requirements below.

• Proven experience designing, simulating and measuring high-speed ICs across multiple analog/mixed-signal domains (serial links, data converters, PLLs, opamps, programmable gain amplifiers, equalization, voltage regulators, output drivers, clock distribution).
• Hands-on experience with mixed-signal simulation and measurement techniques and debugging silicon.
• Strong layout awareness and experience with high-speed/high-frequency layout constraints; ability to coordinate floorplanning for power, ground and signal routing.
• Track record of owning complex IC blocks through design reviews, tape-out and production qualification.
• Excellent cross-functional communication with digital/DSP, package, system and test teams.

Nice-to-have:

• Experience with FinFET/process nodes and high-frequency passive components (inductors, transformers, transmission lines).
• Custom transistor layout and design-for-manufacturability experience.
• ESD laboratory practices and methodology.
• Familiarity with Cadence Virtuoso, Spectre/APS/SpectreX, MATLAB and EM extraction/simulation tools; mixed-signal AMS simulation experience.

Education Requirements

Degree and equivalent-experience guidance found in the posting: BSEE with 12+ years' experience, MS with 8+ years' experience, or PhD with 5+ years' experience, or equivalent practical experience. Fields implied: Electrical Engineering / related technical disciplines. Certifications not specified.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).