Senior Analog Mixed Signal DV Engineer

Role Summary

The Senior Analog Mixed Signal DV Engineer will be a key member of the advanced circuits and power solution team at Texas Instruments, engaging in high-stakes design verification tasks that impact critical customer projects and contribute significantly to TI revenue.

Experience Level

Senior level, requiring a minimum of 5 years of experience in Digital Design Verification.

Responsibilities

The selected candidate will be responsible for:

• Driving verification strategies, creating detailed test plans, and developing comprehensive test benches.
• Ground-up development of the DV environment using UVM components.
• Executing RTL and Gate Level Simulations (GLS) and ensuring full coverage.
• Utilizing technical debugging skills to resolve design and testbench issues.
• Interacting with cross-functional teams to support post-silicon processes.

Requirements

To qualify for this role, you should have:

• Bachelor’s or Master’s degree in Electrical Engineering or Electronics and Communication Engineering.
• Strong expertise in SystemVerilog and UVM methodologies.
• Proficiency with Cadence simulation tools (Xcelium, Vmanager, Jasper Gold).
• Effective communication skills for interaction with cross-functional teams.
• Experience with Formal property verification and understanding of Clock and Reset Domain assertions.

Education Requirements

Bachelor’s or Master’s degree in Electrical Engineering or Electronics and Communication Engineering.

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.