Senior Analog Layout Engineer

Job Title

Senior Analog Layout Engineer

Role Summary

Lead layout engineer responsible for chip- and block-level layout of high-performance analog and mixed-signal products within the High Performance Analog (HPA) PL team in Catania. The role leads layout strategy, integration, verification, and mentoring of other layout engineers.

The position focuses on high-precision, low-noise analog designs including ADCs, precision references, and HV chopper-stabilized amplifiers, and on chip-level floorplanning and physical integration for SoC deliveries.

Experience Level

Senior — typically 10+ years of experience leading analog layout activities in complex ICs.

Responsibilities

Primary responsibilities include layout delivery, floorplanning, verification, and team leadership for analog/mixed-signal SoC projects.

• Drive and deliver floorplan activities at IP and SoC levels.
• Define power-supply strategy and signal distribution between blocks.
• Deliver analog layout blocks and top-level floorplan strategy.
• Lead top-level integration using Mixed-Signal-on-Top flows.
• Lead and schedule a multisite layout team for SoC execution.
• Run physical verifications (DRC/LVS/DFM) and parasitic extraction to ensure high-quality layout deliveries.
• Participate in design reviews, produce documentation, and support product integration.
• Focus on design-for-quality: verification, validation, long-term reliability, and defect reduction.
• Investigate root causes and implement solutions for issues found on first prototypes.
• Provide technical training and write guidelines on layout techniques and best practices.

Requirements

Required skills and experience for immediate contribution and leadership.

Must-have:

• 10+ years leading analog layout activities in complex IC designs.
• Strong expertise in analog layout, device physics, and IC ESD protection strategies.
• Expert user of layout and verification tools such as Cadence Virtuoso (OA, PVS) and Mentor Graphics Calibre.
• Experience delivering advanced floorplan strategies and physical implementation of analog IPs and/or SoC blocks.
• Ability to lead and manage multisite layout teams and collaborate across functions.
• Excellent communication skills and experience working with global cross-functional teams (design, test, program management, quality).

Nice-to-have:

• Proven experience mentoring engineers and producing technical training and guidelines.

Education Requirements

Not specified.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.