Senior Analog Layout Engineer - DPG LPDDR

Job Title

Senior Analog Layout Engineer - DPG LPDDR

Role Summary

Responsible for layout and integration of key analog and mixed-signal blocks for LPDDR designs, ensuring low-noise operation, reliability across PVT corners, and successful first-silicon bring-up on advanced process technologies. The role is based in Hyderabad and works closely with circuit designers, architects, and sign-off teams.

Experience Level

Senior-level. Years of experience not specified in the posting.

Responsibilities

Core responsibilities include layout implementation, integration, and sign-off for sensitive analog and mixed-signal paths.

• Perform layout and integration of essential analog blocks with focus on low-noise performance and reliable operation across PVT corners.
• Apply device-physics knowledge to guide transistor matching, well/substrate engineering, parasitic minimization, and EM/ESD reliability considerations.
• Implement high-speed layout techniques: impedance control, skew matching, shielding, isolation, and crosstalk mitigation.
• Collaborate with circuit designers and architects to identify and mitigate parasitic, noise, and performance risks early in the design cycle.
• Lead post-layout optimization and sign-off activities, including DRC/LVS, EM/IR checks, and correlation of post-layout simulations with silicon or lab data.
• Provide technical mentorship, conduct design reviews, and contribute to layout guidelines and quality improvements.
• Support layout automation and data-driven optimization initiatives where applicable.

Requirements

Must-have technical skills and capabilities; nice-to-have items listed separately.

• Proven experience in analog and mixed-signal layout and block integration for advanced process technologies.
• Strong device-physics expertise applied to layout: transistor matching strategies and parasitic optimization.
• Experience with high-speed/mixed-signal layout techniques (impedance control, skew matching, shielding/isolation).
• Familiarity with sign-off flows: DRC/LVS, EM/IR analysis, and post-layout simulation correlation.
• Ability to work cross-functionally with designers and architects and to lead post-layout debug and optimization.
• Technical leadership and mentoring experience for complex layout blocks.
• Nice-to-have: experience with AI/ML-assisted layout automation, LPDDR-specific layout experience, and deep EM/ESD reliability tool usage.

Education Requirements

B.E. (or equivalent practical experience) in Electronics, Electronics & Communication, or VLSI Engineering. M.Tech in VLSI Build, Microelectronics, or Electronics Engineering is also referenced.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.