Senior Analog Layout Engineer

Job Title

Senior Analog Layout Engineer

Role Summary

Responsible for analog and mixed-signal physical layout of blocks such as PLLs, ADC/DAC, LDOs, VCOs and high-speed interfaces within the Central Engineering group. Work as part of a small analog team to deliver production-ready layouts, support sign-off, and enable reuse across product teams.

Experience Level

Senior-level. Typical experience: 4–6 years in high-speed analog, mixed-signal, and custom layout design.

Responsibilities

Key duties include hands-on layout, verification, and support through tape-out:

• Design and implement analog layout blocks (PLLs, ADC/DAC, LDOs, VCOs, high-speed interfaces).
• Apply advanced layout techniques: device matching, symmetry, common-centroid, shielding, guard rings.
• Floorplanning, placement, and routing of complex analog/mixed-signal blocks; optimize for parasitics, performance, and area.
• Ensure DRC, LVS, and ERC clean layouts and support full sign-off activities.
• Perform post-layout verification including parasitic extraction (PEX), EM/IR, and reliability analysis.
• Handle ECOs and actively support tape-out and release activities.
• Collaborate closely with circuit designers and verification engineers to meet project timelines.

Requirements

Must-have technical experience and skills; listed concisely below.

• 4–6 years of experience in high-speed analog, mixed-signal, and custom layout design.
• Strong understanding of electrical fundamentals and layout behavior, especially in advanced technology nodes.
• Knowledge of local device effects (LDE) and their impact on circuit performance.
• Expertise in device matching, symmetry, clock routing, shielding, and parasitic minimization.
• Familiarity with reliability concerns: EM/IR, latch-up prevention, ESD protection, and power planning.
• Proficiency with Cadence Virtuoso (Layout XL / GXL).
• Familiarity with DRC/LVS tools such as Calibre, ICV, or Pegasus.
• Ability to handle designs across abstraction levels (cell → block → macro).
• Nice-to-have: experience with advanced nodes (2nm/3nm/5nm) and exposure to layout automation or SKILL scripting.
• Must be eligible to access export-controlled technology; non-U.S. applicants may be subject to export license review.
• Interview integrity: use of AI-assisted tools during interviews is not permitted.

Education Requirements

Bachelor's or master’s degree (BE/B.Tech or MS/M.Tech) in Electronics & Communication, Electrical & Electronics Engineering, or a related technical field. (Degree requirement stated in source.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.