Senior AMS Layout Engineer - DPG LPDDR

Job Title

Senior AMS Layout Engineer - DPG LPDDR

Role Summary

Responsible for custom analog and mixed-signal layout of LPDDR PHY blocks within the DPG layout team. Deliver robust, manufacturable layouts for datapath, IO analog frontends, bias/reference circuits, and associated custom digital blocks to enable first-silicon success and high-volume production.

Experience Level

Senior — requires 6+ years of hands-on experience in analog/mixed-signal layout and high-speed interface design, particularly for LPDDR PHYs.

Responsibilities

Design, optimize, and deliver silicon-ready layouts for LPDDR PHYs and related mixed-signal blocks. Collaborate across architecture, circuit, verification, and silicon debug teams.

• Perform custom analog and mixed-signal layout for LPDDR blocks: datapath, bias networks, IO frontends, and reference circuits with attention to noise and matching.
• Execute high-speed LPDDR interface layout addressing skew control, impedance, shielding, crosstalk, and jitter sensitivity.
• Design array-based layouts for DQ/DQS byte lanes, CA lanes, and replica paths ensuring symmetry, pitch matching, and scalability.
• Implement custom digital block layouts within the PHY (training logic, calibration, test/debug) managing clocking and congestion near analog regions.
• Drive layout-aware co-design with circuit designers; incorporate parasitic awareness, timing, noise, IR, and EM requirements early.
• Apply power distribution, grounding, isolation, guard rings, deep-N-well, and decoupling strategies to protect analog and high-speed signals.
• Perform DRC/LVS closure, parasitic extraction reviews, and correlate layout results with simulations; support post-layout optimization and ECOs.
• Contribute to PPA optimization with focus on low power, area efficiency, reliability, and JEDEC compliance.

Requirements

Must-have technical skills and practical experience for day-one contribution. Keep qualifications factual and specific.

• Must-have: Proven expertise in analog and mixed-signal layout for advanced nodes, including high-speed PHYs and serial interfaces.
• Must-have: Experience with LPDDR PHY layout considerations: timing/skew control, impedance matching, shielding, and crosstalk mitigation.
• Must-have: Strong hands-on experience with DRC/LVS closure, parasitic extraction, and silicon correlation.
• Must-have: Demonstrated ability in array-based layout techniques for byte lanes and multi-channel designs; attention to symmetry and repeatability.
• Must-have: Knowledge of power distribution, grounding, domain isolation, and manufacturability constraints; experience driving ECOs.
• Must-have: Effective collaborator across circuits, verification, architecture, and silicon debug teams.
• Nice-to-have: Familiarity with AI/ML techniques for layout automation, data-driven optimization, or debug workflows.

Education Requirements

B. Tech / B. E in Electronics, Electronics & Communications, or VLSI Engineering; M. Tech in Electronics Engineering, Microelectronics, or VLSI Engineering.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.