Senior Advanced Packaging & Power Delivery Engineer

Job Title

Senior Advanced Packaging & Power Delivery Engineer

Role Summary

Lead power-delivery and advanced packaging architecture for next-generation AI accelerators. Own PDN design and analysis across on-die power grids, package and PCB, and drive packaging decisions for multi-chiplet and 2.5D/3D systems.

Work within R&D Custom Design and collaborate with Silicon Engineering and AI Integrated Systems to deliver validated, manufacturable solutions and vendor partnerships.

Experience Level

Senior — typically 7+ years of relevant experience in power delivery and/or advanced packaging design in semiconductor or deep-tech environments.

Responsibilities

Primary responsibilities include:

• Own end-to-end power-delivery design from on-die power grids to package and PCB PDN.
• Define and lead advanced packaging architecture for 2.5D/3D stacking, multi-chiplet integration, and interposer/substrate co-design.
• Perform SI/PI verification and sign-off across the full stack and ensure power and signal integrity targets are met.
• Collaborate with AI Integrated Systems and Silicon Engineering to align packaging and PDN solutions with product requirements.
• Support thermal and system integration reviews for current and future products.
• Develop and maintain PDN methodology, flows, and design guidelines within the Custom Design toolchain.
• Identify and mitigate single-point-of-failure risks in SI/PI workstreams; mentor the team on packaging expertise.
• Engage with external partners, substrate/interposer vendors, and OSATs to co-develop packaging solutions.

Requirements

Required technical skills and experience (concise):

Must-have:

• 7+ years of experience in power delivery and/or advanced packaging design in semiconductor or deep-tech environments.
• Demonstrated expertise in on-die power grid design and package/PCB PDN analysis.
• Hands-on experience with 2.5D and/or 3D IC packaging technologies, multi-chiplet integration, and interposer/substrate co-design.
• Proficiency with industry-standard EDA tools for power integrity, PDN simulation, and package design.
• Ability to communicate complex technical trade-offs to cross-functional stakeholders.
• Strong written and spoken English skills.

Nice-to-have:

• Experience with SI/PI verification and sign-off methodologies.
• Familiarity with thermal modeling and co-simulation for integrated packages.
• Exposure to AI accelerator or custom ASIC design flows.
• Experience collaborating with OSAT partners, substrate vendors, or research institutes.
• Knowledge of advanced-node custom and analog design practices.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a related field; PhD is a plus.

About the Company

Company: Axelera AI

Headquarters: Eindhoven, Netherlands

Deep-tech startup developing a next-generation AI platform (Metis™) and AI accelerators/in-memory compute SoCs. The company has raised $120M, employs around 220 people across multiple countries, and operates European offices while focusing on high-performance AI hardware and software.