Semiconductor Test Engineering Team Leader

Job Title

Semiconductor Test Engineering Team Leader

Role Summary

Lead the manufacturing test strategy and production test readiness for next-generation AI accelerator silicon. You will manage an internal chip test engineering team and coordinate external test development partners to deliver scalable, cost-effective test solutions across ATE bring-up, silicon characterization, yield improvement, and high-volume manufacturing transfer.

This role works across design, DFT, packaging, product engineering and operations; some positions may require export-control eligibility checks. Fractile offers competitive salary, equity, private medical/dental/vision benefits, contributory pension, 25 days holiday plus bank holidays, and life/critical illness insurance.

Experience Level

Senior — typically 8+ years in semiconductor test engineering with leadership or technical lead experience required.

Responsibilities

The core responsibilities focus on test strategy, team leadership, partner management, silicon bring-up, and yield ramp activities.

• Define and drive manufacturing test strategy for high-performance AI accelerator chips (PCIe Gen6, LPDDR, advanced CMOS nodes, advanced packaging).
• Lead and mentor a team of chip test engineers covering test planning, program development, pattern bring-up, and silicon characterization.
• Manage subcontracted test development partners (OSATs, ATE vendors) including scoping, technical oversight, schedule tracking and quality control.
• Define test software architecture, DFT usage, and pattern development approaches for high-speed logic, SRAM/DRAM and HSIO blocks.
• Oversee ATE bring-up, correlation, shmooing, corner and stress testing, failure analysis, and debug activities.
• Collaborate with design, DFT, packaging, product engineering and validation to ensure test coverage and manufacturability.
• Develop KPIs and metrics for test coverage, yield, time-to-test, subcontractor performance and cost optimization.
• Drive continuous improvement in test methodologies, automation, data analytics and debug infrastructure.
• Ensure robust test flows for advanced packaging (thermal, interposer/bridge connectivity, TSV and die-to-die IO testing) and support qualification and HVM transfer.

Requirements

Must-have technical skills and experience for immediate impact on production test and ramp activities.

• 8+ years in semiconductor test engineering, including leadership or technical lead roles.
• Hands-on ATE test development experience (e.g., Advantest 93K, Teradyne).
• Strong understanding of DFT (scan, ATPG, LBIST, MBIST), memory testing, and high-speed interface testing.
• Proven experience managing external test development partners or OSATs.
• Proven ability to lead, mentor and scale test engineering teams.
• Experience with advanced CMOS nodes and awareness of advanced packaging test challenges.
• Expertise in silicon debug, characterization, correlation between ATE and system-level environments.
• Effective cross-functional collaboration skills with design, architecture, packaging, product engineering and operations.

Nice-to-have / preferred:

• Experience with AI/ML accelerator chips or other high-performance compute ICs.
• Prior involvement with PCIe Gen5/Gen6 and LPDDR4/5/6 test methodologies.
• Familiarity with signal-integrity-aware test development and high-speed IO margining.
• Experience with chiplets, 2.5D/3D IC test flows or heterogeneous integration.

Education Requirements

Not specified.

About the Company

Company: Fractile

Headquarters: London, UK

Fractile is on a mission to revolutionize AI by developing silicon, systems, and software that enable the fastest execution of advanced models at lower costs. Established in 2022, the company has rapidly expanded, fostering a collaborative culture in its London and Bristol offices. With a focus on innovation in ML/AI IC product development, Fractile combines hardware and software to deliver high-impact solutions for data center applications.