Semiconductor Product Engineering Team Leader

Job Title

Semiconductor Product Engineering Team Leader

Role Summary

Lead product engineering for manufacturing test and production readiness of next-generation AI accelerator silicon. Manage an internal test engineering team and coordinate external test development partners to deliver robust, scalable, and cost-effective test solutions across silicon bring-up, characterization, and high-volume manufacturing ramp.

This role focuses on test strategy for advanced CMOS nodes, high-speed IO, memory, and advanced packaging (2.5D/3D/chiplets) to ensure manufacturability, yield, and test automation at scale.

Experience Level

Senior role. The team requires extensive hands-on and leadership experience; the posting requests 8+ years in semiconductor test engineering including leadership or technical lead roles.

Responsibilities

Primary responsibilities include ownership of test strategy, team leadership, and coordination with design and manufacturing to ensure production readiness.

• Define and drive manufacturing test strategy for AI accelerator devices (high-speed IO, memory, advanced packaging).
• Lead and mentor a team responsible for test planning, program development, pattern bring-up, and silicon debug.
• Manage external test development partners (OSATs, ATE vendors): scoping, technical oversight, schedules, and deliverable quality.
• Specify test software architecture, DFT usage, and pattern development for logic, SRAM, DRAM, and HSIO blocks.
• Oversee ATE bring-up, correlation, failure analysis, shmooing, corner and stress testing, and yield-improvement activities.
• Drive test flows and validation for advanced packaging (interposer/bridge, TSVs, die-to-die IO, thermal considerations).
• Define KPIs for subcontractor performance, test coverage, time-to-test, yield, and cost optimization.
• Improve test methodologies, automation, data analytics, and debug infrastructure.
• Support qualification, reliability testing, and transfer to high-volume manufacturing.

Requirements

Must-have technical skills and leadership experience; preferred items listed separately.

• 8+ years in semiconductor test engineering with leadership or technical lead experience.
• Hands-on ATE test development experience (e.g., Advantest 93K, Teradyne Ultraflex or similar).
• Strong understanding and practical experience with DFT (scan, ATPG, LBIST, MBIST), memory testing, and high-speed interface testing.
• Proven experience managing external partners/OSATs and coordinating cross-functional teams (design, packaging, manufacturing).
• Expertise in silicon debug, characterization, correlation between ATE and system-level environments.
• Experience with advanced CMOS node challenges and test implications of advanced packaging.
• Demonstrated ability to lead and mentor test engineering teams and to define measurable KPIs.

Nice-to-have:

• Experience with AI/ML accelerator chips or other high-performance compute ICs.
• Prior involvement with PCIe Gen5/Gen6 or LPDDR4/5/6 test methodologies.
• Familiarity with signal-integrity-aware test development and high-speed IO margining.
• Experience with chiplets, 2.5D/3D IC test flows, or heterogeneous integration.

Education Requirements

BS, MS, or PhD in Electronics or Electrical Engineering or a related technical field (e.g., Computer Engineering, Physics). The posting specifies these degree levels; no specific certification requirements or explicit "equivalent experience" language was provided.

About the Company

Company: Fractile

Headquarters: London, UK

Fractile is on a mission to revolutionize AI by developing silicon, systems, and software that enable the fastest execution of advanced models at lower costs. Established in 2022, the company has rapidly expanded, fostering a collaborative culture in its London and Bristol offices. With a focus on innovation in ML/AI IC product development, Fractile combines hardware and software to deliver high-impact solutions for data center applications.