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Semiconductor Design Engineer

LanceSoft
May 21, 2026
Full-time
On-site
Folsom, California, United States
$72,000 - $108,000 USD yearly
Physical Design Jobs, Level - Senior

Job Title

Semiconductor Design Engineer

Role Summary

Senior semiconductor design engineer responsible for IO architecture, floor-planning, custom circuit and datapath design, and defining packaging/board connectivity for advanced chips. Works cross-functionally with architecture, packaging, assembly, and board teams to deliver power-efficient, manufacturable solutions.

Experience Level

Senior-level. Requires 10+ years of semiconductor design experience with a minimum of 8 years focused on IO and architecture-related work.

Responsibilities

Primary responsibilities include translating product requirements into physical implementations and driving IO and floor-planning decisions across chip and package boundaries.

  • Define and drive chip-level IO architecture, including clocking and voltage-domain crossing.
  • Lead floor-planning and align physical layout with electrical IO requirements.
  • Design, modify and evaluate semiconductor circuits and components; produce layout, circuit checks, documentation, and specifications.
  • Influence signaling strategy, power rail/bump-patterning, and ESD requirements affecting package and board design.
  • Develop custom datapath definitions and power-efficient circuit designs.
  • Collaborate with packaging, assembly, and board connectivity teams to ensure integration and manufacturability.
  • Conduct regular project check-ins to align priorities in dynamic program environments.

Requirements

Must-have technical skills and experience required to perform the role.

  • 10+ years of semiconductor design experience; at least 8 years in IO/architecture-focused roles.
  • Deep expertise in IO architecture: clocking schemes and voltage-domain crossing.
  • Proven experience with floor-planning and physical/package/board design considerations.
  • Experience with power rail/bump-patterning and ESD definition.
  • Familiarity with DDR/HPM and platform-level architecture.
  • Proficiency with Cadence tools (Virtuoso, Allegro) and MOM file usage.
  • Experience creating schematic definitions and pioneer circuits for floor plans.
  • Strong cross-functional collaboration skills across architecture, packaging, and board teams.

Nice-to-have:

  • System-level architecture exposure and advanced clocking/exporting expertise.
  • Proven experience working on fast-paced, complex semiconductor programs.

Education Requirements

Not specified.


About the Company

Company: LanceSoft

Technology staffing and consulting firm providing IT and engineering recruitment, talent solutions, and workforce services to clients across industries.

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Date Posted: 2026-05-19