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Semiconductor Design Engineer

LanceSoft
May 25, 2026
Full-time
On-site
Folsom, California, United States
$72,000 - $108,000 USD yearly
Physical Design Jobs, Level - Senior

Job Title

Semiconductor Design Engineer

Role Summary

Lead chip-level IO architecture, floor-planning, and custom circuit design for advanced semiconductor products. Define IO, clocking, voltage domain crossings, power schemes, and packaging/board connectivity while coordinating with architecture, packaging, and board teams.

Experience Level

Senior-level. Typical requirement: 10+ years semiconductor design experience with at least 8 years focused on IO and architecture work.

Responsibilities

Core responsibilities include design, verification, and cross-functional alignment on IO and physical implementation.

  • Perform chip layout, circuit checks, documentation, and specification development.
  • Review product requirements and logic diagrams to define device behavior.
  • Design, fabricate, modify, and evaluate semiconductor devices and components.
  • Drive IO definition, clocking strategy, and voltage domain crossing implementation.
  • Lead floor-planning ensuring alignment with physical and electrical IO requirements.
  • Define signaling, power rail and bump-patterning, and ESD requirements affecting package and board design.
  • Develop custom datapath definitions and power-efficient circuit designs.
  • Collaborate with assembly, packaging, and board connectivity teams to ensure integration.
  • Conduct regular project check-ins to align priorities in a dynamic program.

Requirements

Must-have technical skills and experience.

  • 10+ years semiconductor design experience; minimum 8 years in IO/architecture.
  • Deep expertise in IO architecture including clocking and voltage domain crossing.
  • Proven floor-planning experience and knowledge of physical packaging and board/package design.
  • Experience with power rail/bump-patterning and ESD definition.
  • Familiarity with DDR/HPM and platform architecture.
  • Proficiency with Cadence tools (Virtuoso, Allegro) and experience with MOM files.
  • Experience developing pioneer circuits and schematic definitions for floor plans.
  • Strong cross-functional collaboration skills across architecture, packaging, and board teams.

Preferred:

  • System-level architecture exposure.
  • Advanced clocking and exporting expertise.
  • Proven track record in dynamic, fast-paced semiconductor programs.

Education Requirements

Not specified.


About the Company

Company: LanceSoft

Technology staffing and consulting firm providing IT and engineering recruitment, talent solutions, and workforce services to clients across industries.

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Date Posted: 2026-05-23