Scale-Up Ethernet Engineer

Job Title

Scale-Up Ethernet Engineer

Role Summary

Design, validate, and operate Ethernet-based scale-up rack systems that connect multiple AI accelerators into a single high-performance compute unit. The role covers link bring-up, switch-fabric tuning, workload-driven performance and reliability analysis, rack management and observability, and verification automation across hardware, firmware, drivers, NOS, and orchestration layers.

The engineer will collaborate across SoC, firmware, switch, and system teams and build repeatable rack bring-up and test infrastructure, using automation and AI-assisted workflows to scale verification and lab operations.

Experience Level

Mid-level. No specific years stated; requires practical experience in data-center Ethernet, SoC firmware/drivers, and rack/cluster bring-up.

Responsibilities

Primary responsibilities include hands-on integration, verification, and operationalization of scale-up Ethernet racks:

• Validate Scale-Up Ethernet endpoints from pre-silicon prototypes through production silicon, including integration with SoC buses (e.g., AXI), DMA, memory maps, interrupts, and firmware.
• Tune NICs and switch fabric (buffers, queues, PFC, LLR/CBFC, ECN) and evaluate scale-up switches to improve congestion behavior and stability.
• Perform cross-layer root-cause analysis using packet captures, counters, logs, and telemetry to separate hardware, firmware, driver, software, and fabric issues.
• Build and run clusters with collective communication and LLM inference workloads to measure bandwidth, latency (including tail latency), and stability; reproduce and debug corner cases.
• Verify link interoperability and stability across MAC/PCS/FEC/SerDes, optical modules (DR/FR), DAC/AEC/AOC cables, and switch ports; validate CMIS module state and behavior under resets and temperature variation.
• Design and implement rack management: inventory (FRU/firmware/modules), power sequencing and remote control, firmware update flows, and APIs for orchestrators using standards (Redfish, PLDM, gNMI/YANG, OpenRMC patterns).
• Define observability and RAS: collect time-series for power/temperature/links, design fail-safe recovery, and validate via fault-injection.
• Lead PoC migration of rack verification to OCP-standard configurations (Open Rack etc.) and run staged verification from link bring-up to full rack integration.
• Automate test execution, remote console and power control, result collection, long-duration stability tests, and documentation; enable multi-agent workflows and equipment reservation/control to prevent conflicts.

Requirements

Must-have:

• Practical understanding of data-center Ethernet (switches, lossless fabrics, RDMA) and experience configuring/debugging network devices in Linux.
• Experience developing or debugging semiconductor system software at register/memory-map level (SoC firmware, device drivers, silicon bring-up/diagnostics).
• Hands-on experience with rack- or cluster-level bring-up, integration verification, and performance analysis involving servers, switches, and accelerators.
• Ability to automate test execution, device control, and log collection using Python or shell scripting.
• Skill in hypothesis-driven debugging using packets, logs, and performance counters to reproduce and isolate issues.
• Experience collaborating across hardware, firmware, software, and vendor teams and documenting verification methods and results clearly.
• Comfort using AI tools (LLMs/coding agents) in workflows and validating agent-produced results as part of verification and automation.

Nice-to-have (preferred skills):

• Experience with 100G–800G link bring-up, performance evaluation, or interoperability testing.
• Familiarity with MAC/PCS/FEC/SerDes, QSFP-DD/OSFP modules, DAC/AEC/AOC cables, and CMIS module management.
• Experience tuning lossless Ethernet fabrics (PFC, ECN, buffer/queue configuration) and working with Tomahawk-class switches or SONiC NOS internals.
• Experience with Redfish/OpenBMC, PLDM/MCTP, OpenRMC and rack manager or fleet management systems.
• Background building hardware test labs, CI-based regression suites, telemetry, or long-duration stability testing infrastructure.
• Experience designing multi-agent orchestration, equipment-control APIs, and session/task management for automated workflows.

Education Requirements

Bachelor's degree in Computer Engineering, Electrical/Electronic Engineering, Computer Science, or a related field, or equivalent practical experience.

About the Company

Company: FuriosaAI

Headquarters: Seoul, South Korea

FuriosaAI develops high-performance, energy-efficient AI inference hardware and software. Founded in 2017 by semiconductor and AI engineers, the company builds AI-native compute platforms to reduce AI energy and operational costs and operates globally with offices in Korea, Silicon Valley, and an R&D lab in Lisbon.