RTL Synthesis and Constraints Lead

Role Summary

This position is focused on directing the timing constraint design and achieving sign-off in close collaboration with the Physical Design team for a system on chip (SoC) subsystem. Candidates should have demonstrated experience in digital design and SOC quality assurance.

Experience Level

Ideal candidates will possess 7-10 years of relevant experience, particularly in a role dedicated to SOC timing leadership.

Responsibilities

The main responsibilities include:

• Developing and implementing timing constraints for SoC subsystems.
• Working alongside RTL leads to leverage and establish best practices for constraint development.
• Collaborating with the Physical Design and DFT (Design for Test) teams to ensure timing sign-off.
• Ensuring timely project delivery while maintaining required quality standards.
• Providing robust technical solutions to both internal and external stakeholders.

Requirements

Applicants must demonstrate proven experience in roles focusing on timing closure of subsystem IP, strong analytical skills, and effective communication abilities.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is essential.