RTL / Microarchitecture Engineers

Job Title

RTL / Microarchitecture Engineers

Role Summary

Work on RTL and microarchitecture for RISC‑V processor subsystems at advanced process nodes. Team focus areas include processor pipeline, instruction and data caches, L2 pipeline, and a custom memory controller. The role requires engineers who can take architecture-level requirements through to RTL implementation and delivery.

Experience Level

Senior — 8+ years of relevant experience.

Responsibilities

Primary responsibilities include designing, implementing and verifying RTL for processor blocks and collaborating with architecture, verification and backend teams.

• Implement and optimize RTL for processor pipeline stages.
• Design and implement d-cache, i-cache and L2 pipeline logic in RTL.
• Develop RTL for a custom memory controller and related interfaces.
• Translate microarchitecture specifications into synthesizable Verilog.
• Create and maintain unit-level verification and scripting to support regression.
• Collaborate with architects, verification and physical design to meet timing, area and power targets.

Requirements

Must-have technical skills and experience.

• 8+ years in RTL or microarchitecture roles.
• Proven experience with Verilog and RTL design.
• Strong scripting skills for automation (e.g., Python, Tcl, Perl).
• Experience with RISC‑V processor design or analogous CPU microarchitecture (pipelines, caches, memory controllers).
• Fluency in English (approximately C1 level).
• Ability to take ownership of end-to-end RTL deliverables and work independently.

Nice-to-have:

• Experience with advanced process node design constraints and optimization.
• Knowledge of formal verification methods or UVM-based verification flows.

Education Requirements

Minimum Bachelor's degree in Computer Science (as stated in the posting).

About the Company

Company: Semidynamics

Headquarters: Barcelona, Spain

Semidynamics is a company specializing in infrastructure verification and automation solutions. They focus on optimizing resources and enhancing continuous integration processes in design verification. The team collaborates to maintain regression test infrastructure and develop efficient workflows.