RTL Design & Verification Staff Engineer
SynopsysJob Title
RTL Design & Verification Staff Engineer
Role Summary
The RTL Design & Verification Staff Engineer will be responsible for designing and verifying RTL for ASICs. This role is integral to the development of cutting-edge digital designs and involves collaboration with cross-functional teams.
Experience Level
Mid-level, with a minimum of 5 years of experience in RTL design and verification.
Responsibilities
Key responsibilities include:
- Designing RTL for innovative ASIC products.
- Verifying designs using simulation and formal verification methodologies.
- Collaborating with project teams to ensure quality and timely delivery.
- Participating in design reviews and providing constructive feedback.
- Debugging complex design issues in a development environment.
Requirements
The ideal candidate should meet the following requirements:
- Strong experience in digital design and verification.
- Proficiency in SystemVerilog and verification methodologies.
- Experience with ASIC design flow and EDA tools.
- Ability to work effectively in a team-oriented environment.
- Nice to have: exposure to low-power design techniques.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
