RTL Design Engineer
Design RTL for advanced-node mixed-signal ASICs in Teradyne's Silicon Technology Engineering (STE) Digital ASIC Group. Collaborate with chip architects, analog engineers, verification, and physical design teams across specification, micro-architecture, RTL, verification, timing closure, and silicon bring-up.
Deliver high-quality RTL for large mixed-signal SOCs and memory test instruments used in production semiconductor test systems.
Senior β typically requires 5+ years of RTL/ASIC design experience.
Primary responsibilities include design, integration, verification collaboration, and silicon bring-up:
Must-have technical skills and experience:
Nice-to-have:
Bachelor of Science (BSEE) or Master of Science (MSEE) in Electrical Engineering or a related field is specified. The posting indicates 5+ years of relevant experience.
Company: Teradyne
Headquarters: North Reading, Massachusetts, United States
Teradyne is a global leader in test and automation solutions, ensuring every electronic device performs effectively. Their sophisticated technology helps manufacturers develop and deliver products quickly and cost-effectively, supporting various industries worldwide. With a strong commitment to fostering a diverse and inclusive work environment, Teradyne encourages innovation and collaboration among its employees.
