Job Title
RTL Design Engineer
Role Summary
Design, specify, model, and implement RTL for advanced PLL IPs. Work within an ASIC/IP design team to produce Verilog RTL, microarchitecture specifications, and supporting scripts across the design flow.
The role interfaces with verification and physical-design teams to ensure functional correctness, timing closure, power optimization, and support for silicon bring-up.
Experience Level
Mid-level — typically requires about 5+ years of progressive RTL design experience.
Responsibilities
Key duties include:
- Analyze complex digital design problems and propose architectural solutions.
- Develop Verilog RTL and behavioral models for current and future IPs.
- Create microarchitecture specifications and drive ASIC design flows with supporting scripts.
- Collaborate with Design Verification and Physical Design teams for correctness, timing closure, and implementation.
- Deliver design optimizations and power-saving enhancements; support silicon bring-up and diagnostics.
Requirements
Essential and preferred technical skills.
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Must-have: 5+ years of RTL design experience.
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Must-have: Strong proficiency in Verilog and RTL design methodologies.
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Must-have: Proven ability to analyze complex digital problems and drive tasks independently to completion.
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Must-have: Ability to mentor junior engineers and communicate effectively within a team.
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Nice-to-have: Experience in analog mixed-signal design from specification to silicon.
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Nice-to-have: Experience with high-speed interfaces (DDR, GDDR, HBM, SERDES) and multi-power/clock-domain designs.
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Nice-to-have: Familiarity with ASIC CAD tool flows for simulation, synthesis, STA, CDC, UPF, and power estimation.
Education Requirements
Relevant academic background; a Master’s degree is preferred. Specific degree fields were not detailed in the posting.
About the Company
Company: Tanisha Systems
Engineering services company focused on wireless communications, FPGA development, and embedded systems, supporting 5G/6G and broadband technology projects.

Date Posted: 2026-07-13