RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

Design RTL for complex digital subsystems used in large-scale AI data center infrastructure. Translate architecture into efficient, synthesis-ready microarchitectures and collaborate with verification, physical design, and architecture teams to deliver silicon-ready designs.

Small engineering team headquartered in Palo Alto with a mix of remote and on-site operations across the U.S. and Canada.

Experience Level

Mid-level - approximately 5 years of RTL design experience required.

Responsibilities

Primary responsibilities include RTL design, cross-functional collaboration, and ensuring designs are verifiable and synthesis-ready.

• Design and implement RTL using Verilog/SystemVerilog for complex digital subsystems.
• Translate architectural specifications into clean, scalable microarchitectures.
• Collaborate with architecture, verification, and physical design teams to ensure correctness and closure.
• Develop reusable RTL with strong coding standards and documentation.
• Perform linting, CDC analysis, and prepare designs for synthesis.
• Support integration and debug in simulation and early silicon environments.
• Participate in design reviews and provide technical input on tradeoffs.
• Work with verification teams to ensure comprehensive functional coverage and assist in timing closure.
• Contribute to continuous improvement of design methodologies, flows, and tools.

Requirements

Key must-have skills and a short list of desirable qualifications.

• Must-have: Approximately 5 years of RTL design experience.
• Must-have: Strong hands-on experience with Verilog/SystemVerilog.
• Must-have: Solid understanding of synchronous digital design and microarchitecture principles.
• Must-have: Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE).
• Must-have: Familiarity with synthesis, timing constraints, and physical-design considerations.
• Must-have: Strong analytical, problem-solving, written and verbal communication skills; high attention to detail.
• Must-have: Ability to work independently and manage tasks to completion, including using AI-assisted workflows while verifying AI-generated outputs.
• Nice-to-have: Experience with high-performance systems (AI/ML accelerators, networking, SoCs), low-power techniques, DFT, scripting (Python, Tcl), and advanced process nodes.
• Nice-to-have: Experience using AI coding agents in RTL workflows and converting design experience into reusable AI guidance.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field as stated in the posting. No certifications or equivalent-experience language was specified.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.