RTL Design Engineer

Role Summary

The RTL Design Engineer position is focused on leading digital design and verification for a range of analog mixed-signal IP and IOs, including advanced AI programs. The role requires collaboration with a team of engineers, leveraging a culture of cooperative growth and development.

Experience Level

MS degree with a minimum of 10 years of relevant industry experience in digital design and verification.

Responsibilities

The key responsibilities include:

• Defining digital architecture and verification strategies for complex AMS and IO subsystems.
• Designing, synthesizing, and verifying RTL using Verilog/SystemVerilog.
• Analyzing, debugging, and resolving Lint and CDC issues in designs.
• Driving design convergence to timing closure through RTL optimization strategies.
• Conducting formal verification with tools like Synopsys Formality and Cadence Conformal.
• Generating timing constraints for Synthesis and STA at the block-level and SoC top-level.
• Driving comprehensive test plans to ensure design quality.
• Collaborating with cross-functional teams, including circuit designers and SoC-level integration teams.
• Creating and maintaining detailed specification, design, and verification documentation.

Requirements

The following skills and experiences are required:

• Hands-on experience with digital implementation from RTL synthesis to timing closure.
• Deep understanding of timing analysis techniques and Liberty models.
• Proficiency in using Tessent tools for DFT insertion and verification.
• Ability in scripting with Perl, Python, and Tcl.
• Self-motivated with strong problem-solving abilities and attention to detail.
• Excellent teamwork skills for effective collaboration.

Education Requirements

Master's Degree (MS) is required, along with 10+ years of relevant experience in the industry.