Job Title
RTL Design Engineer
Role Summary
Design and implement register-transfer level (RTL) for advanced PLL IPs. Work on microarchitecture, RTL implementation, and ASIC design flows while collaborating with verification and physical design teams to achieve functional correctness and timing closure.
Support silicon bring-up, deliver performance and power optimizations, and diagnose post-silicon issues.
Experience Level
Mid-level β typically requires 5+ years of RTL design experience.
Responsibilities
The primary responsibilities include:
- Analyze complex digital design problems and propose architectural solutions.
- Develop Verilog RTL and functional behavioral models for current and future IPs.
- Create microarchitecture specifications and drive ASIC design flows with supporting scripts.
- Collaborate with design verification and physical design teams to ensure functional correctness, timing closure, and proper implementation.
- Deliver design improvements, optimization, and power-saving enhancements; support silicon bring-up and diagnostics.
Requirements
Must-have technical skills and experience:
- 5+ years of progressive RTL design experience.
- Strong proficiency in Verilog and RTL design methodologies.
- Proven ability to analyze complex digital problems and independently drive tasks to completion.
- Experience mentoring junior engineers and communicating effectively within a team.
Nice-to-have:
- Analog mixed-signal design experience from specification to silicon.
- Experience with high-speed interfaces (DDR, GDDR, HBM, SERDES) and multi power/clock domain designs.
- Familiarity with ASIC CAD tools for simulation, synthesis, STA, CDC, UPF, and power estimation.
Education Requirements
Master's degree preferred; relevant academic background in a technical discipline is expected. (Posting notes a Master's is preferred but does not specify exact fields or state explicit equivalent-experience language.)
About the Company
Company: Tanisha Systems
Engineering services company focused on wireless communications, FPGA development, and embedded systems, supporting 5G/6G and broadband technology projects.

Date Posted: 2026-07-15