RISCV Infra System IP DV - Sr Staff Engineer

Job Title

RISCV Infra System IP DV - Sr Staff Engineer

Role Summary

Senior verification engineer responsible for design verification of RISC-V infrastructure and system IP. The role sits in the IP Design Verification team and focuses on planning and executing verification strategies, developing UVM/SystemVerilog testbenches, and driving coverage closure across simulation and emulation.

Experience Level

Senior - role expects an experienced verification engineer. Typical experience guidance in the posting: Bachelor's +6 years, Master's +5 years, or PhD +4 years of relevant hardware engineering or verification experience.

Responsibilities

Core duties include designing and executing verification plans, implementing verification infrastructure, and collaborating on debug and coverage closure.

• Define verification strategy and develop test plans to cover design feature sets.
• Design and implement UVM/SystemVerilog testbenches and collateral (checkers, trackers, scoreboards, assertions, functional coverage).
• Create and run regression suites; analyze failures and drive bug fixes.
• Work with system architects, design, and emulation teams on failure debug and coverage closure.
• Verify interconnect and bus protocols (CHI, AHB, AXI, ACE, ACE-Lite) and related interconnect concepts.
• Validate system-level behavior for RISC-V/ARM architectures, memory management, virtual memory, coherency, and virtualization.
• Collaborate across a global engineering organization and document verification results.
• Support post-silicon bring-up and HW-SW debug when applicable (preferred).

Requirements

Must-have technical skills and domain experience; items listed as preferred where noted.

• Proven IP/sub-system design verification experience using UVM and SystemVerilog.
• Experience building testbenches, assertions, scoreboards, checkers, trackers, and functional coverage.
• Strong debug skills for regression failures and root-cause analysis.
• Familiarity with bus and interconnect protocols (CHI, AHB, AXI, ACE, ACE-Lite).
• Knowledge of RISC-V and ARM system architecture, memory management, virtual memory, coherency protocols, and virtualization.
• Proficient communication and collaboration skills for large, distributed teams.
• Desirable: scripting for automation (Python or Perl) and experience with Gen AI tools for productivity improvements.
• Desirable: post-silicon bring-up and HW-SW debug experience.

Education Requirements

Bachelor's, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, Electronics & Communication, Microelectronics, or a related engineering field - or equivalent practical experience as specified in the posting (e.g., Bachelor +6 years, Master +5 years, PhD +4 years of relevant hardware engineering/verification experience).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.