RISC-V Infra System IP DV - Senior Lead Engineer

Job Title

RISC-V Infra System IP DV - Senior Lead Engineer

Role Summary

Lead verification of RISC-V infrastructure IP and subsystems. Define verification strategy, develop UVM/SystemVerilog testbenches and test plans, drive coverage closure, and collaborate with architects, design, emulation and validation teams to deliver silicon-quality IP.

Experience Level

Senior - typically 3 to 15 years of IP/subsystem design verification experience. (Minimum experience guidance available via degree-based combinations.)

Responsibilities

Key responsibilities include:

• Design and implement UVM/SystemVerilog verification environments (checkers, trackers, scoreboards, assertions, functional coverage).
• Create test plans and test cases to exercise design features and drive code/functional coverage closure.
• Run regressions, analyze failure signatures, debug issues and coordinate fixes with design and emulation teams.
• Collaborate with system architects and cross-functional teams on feature verification and debug activities.
• Verify interconnect and bus protocol behavior (CHI/AHB/AXI/ACE/ACE-Lite) and related system interactions.
• Participate in cross-team reviews to ensure verification completeness and handoff readiness.

Requirements

Core technical requirements and preferred skills.

• Must-have: Extensive IP/subsystem verification experience using UVM and SystemVerilog; experience building verification infrastructure (checkers, scoreboards, coverage).
• Must-have: Experience developing test plans and driving functional/code coverage closure across multiple testbench levels.
• Must-have: Strong debug skills for regression failures and root-cause analysis; experience working with emulation and design teams.
• Must-have: Familiarity with bus protocols and interconnect concepts (CHI, AHB, AXI, ACE, ACE-Lite).
• Must-have: Knowledge of system architecture (ARM and RISC-V), memory management/virtual memory, coherency protocols and power-management fundamentals.
• Must-have: Strong communication and collaboration skills for working with large, global teams.
• Preferred / Nice-to-have: Post-silicon bring-up and HW–SW debug experience.
• Preferred / Nice-to-have: Proficiency in scripting for automation (Python or Perl); Gen AI skills are desirable.

Education Requirements

Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, Electronics & Communication, Microelectronics, or a related engineering field; or equivalent practical experience. Degree-based minimum experience: Bachelor's +3 years, Master's +2 years, PhD +1 year.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.