RISC-V CPU Design Verification (Multiple Levels) - Pune
QualcommJob Title
RISC-V CPU Design Verification (Multiple Levels) - Pune
Role Summary
Hardware verification engineer role focused on functional and power-aware verification of RISC-V CPU cores and CPU-based SoCs. The role works within the hardware engineering/ASIC verification team to develop verification plans, implement tests, and validate CPU features across simulation, emulation and silicon bring-up.
Experience Level
Multiple levels (typically mid-career to senior). Experience guidance in the posting varied; example ranges mentioned include roughly 1+ to 4+ years depending on level.
Responsibilities
Primary responsibilities include planning, implementing and executing verification activities for CPU designs and collaborating with adjacent teams to close verification gaps.
- Develop and execute verification plans for CPU units and features.
- Create testbenches, checkers, assertions, and stimulus generators for simulation.
- Implement assembly and C tests to validate CPU architecture and microarchitecture.
- Use simulation, formal methods and emulation to validate functionality and power behavior.
- Enable and run verification on emulators and FPGA platforms; collaborate with emulation teams.
- Debug and triage failures observed in simulation, emulation and silicon.
- Collaborate with system architects, RTL designers, software teams and SoC integration teams to validate system use cases.
Requirements
Must-have technical skills and experience for effective contribution to CPU verification projects.
- Hands-on experience in CPU/processor verification (RISC-V experience preferred; experience with other ISAs such as ARM, x86, MIPS, POWER is relevant).
- Proficiency in C/C++ and experience writing assembly tests for verification.
- Experience with RTL and verification languages: Verilog/SystemVerilog and related verification methodologies.
- Experience with simulation and emulation flows and using FPGA platforms for verification.
- Experience verifying power-management features (clock gating, power gating, UPF, DVFS/DCVS) and related functional impacts.
- Strong debugging skills for failures across simulation, emulation and silicon.
- Must be able to work cross-functionally with architects, design, software and SoC teams.
- Nice-to-have: experience with formal verification and assertions, DFT and structural debug (JTAG, IEEE1500, MBIST), and advanced verification techniques.
Education Requirements
Accepts Bachelor's, Master's or PhD in Computer Science, Electrical/Electronics Engineering, or related engineering fields. The posting also referenced BE/BTech qualifications. The posting allowed degree holders with varying experience levels and indicated alternatives such as equivalent practical experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
