Research Scientist - Loop Engineering and AI Infrastructure

Job Title

Research Scientist - Loop Engineering and AI Infrastructure

Role Summary

Full-time research scientist role on the San Jose team focused on loop engineering, AI infrastructure research, or both. The role creates reproducible co-design flows and system-level measurements that connect memory/device behavior to SoC design automation and AI performance.

Own research questions, methods, experiments, and written deliverables; deliver measured, repeatable results that guide design decisions.

Experience Level

Mid-level (Research Scientist). The team expects candidates with a record of completing research projects that produce measured, written outcomes.

Responsibilities

Deliver research, build automated co-design flows, and quantify system-level effects of memory and device behavior.

• Design and implement closed-loop co-design flows that run SoC tools, simulators, software builds, physical-design feedback, and AI agents.
• Automate SoC, RTL, or physical-design flows and enable reusable design-space exploration.
• Build flows using appropriate languages and tools (examples: Chisel, XLS, simulators, ASIC/FPGA CAD).
• Measure and compare designs on power, speed, silicon area, correctness, workload performance, and search cost; document results for reproducibility.
• Study AI system stacks from storage and memory devices through controllers, interconnects, and host software to identify bottlenecks and impacts on model quality, latency, throughput, and energy.
• Evaluate compute-memory architectures such as near-memory, in-memory compute, computational storage, and disaggregated memory.

Requirements

Must-have technical skills and demonstrable research experience; candidates may be assigned to loop-engineering work, AI-infrastructure work, or both.

• Proven record of taking a research question to a measured, written result.
• Strong proficiency in Python.
• Loop-engineering track: experience automating SoC, RTL, or physical-design flows and designing interfaces between design tools for reusable flows.
• AI-infrastructure track: research experience linking storage/memory device behavior or system bottlenecks to host-level AI workload performance.

Preferred (nice-to-have):

• Hands-on experience with AI-assisted hardware/software co-design frameworks (e.g., CHIA) or similar agentic/scripted flows.
• Proficiency with Chisel, XLS, RISC-V SoC integration, RTL simulation, or FPGA prototyping.
• Experience with commercial ASIC flows and with reading timing, power, and area reports; familiarity with architecture simulators.
• Background in memory/storage reliability (device noise, ECC, endurance, error models); publications or patents in related areas.

Education Requirements

Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science. Bachelor’s candidates should include research depth in computer architecture, computer systems, VLSI, or electronic design automation.

About the Company

Company: SK hynix America

Headquarters: Icheon, South Korea

U.S. subsidiary of SK hynix, a global semiconductor company specializing in DRAM and NAND flash memory and related memory solutions for mobile devices, data centers, and consumer electronics. Focuses on advanced memory technologies, AI applications, and high-performance storage.