Reliability Verification (RV) Design Methodology and Automation Engineer

Job Title

Reliability Verification (RV) Design Methodology and Automation Engineer

Role Summary

Develop, enhance, and maintain scalable automation, flows, and methodologies for electromigration (EM) and IR drop (EMIR) analysis and signoff for advanced FPGA designs. Work closely with design, physical implementation, QRE, project, and foundry teams to define signoff criteria and ensure power integrity and reliability closure.

The role combines tool/flow development, project signoff execution, and cross-team methodology deployment to enable reliable power signoff across technology nodes.

Experience Level

Senior — typically requires 6+ years of relevant EMIR/power integrity experience.

Responsibilities

Primary responsibilities span EMIR tool/flow development, project signoff execution, integration with design flows, and continuous improvement of methodologies and automation.

• Design, develop, and deploy EMIR flows and methodologies for silicon programs.
• Build and maintain automation and infrastructure for EMIR setup, execution, data processing, and reporting.
• Standardize EMIR methodologies across projects and technology nodes.
• Enable and support signoff use of tools such as Voltus and Redhawk-SC; integrate EMIR into broader design and signoff flows.
• Execute project-level EMIR signoff and drive reliability closure in coordination with PD and QRE teams.
• Analyze EMIR violations, define mitigation strategies, and drive systematic closure with physical design teams.
• Collaborate with QRE, project teams, and foundries to define/refine signoff specifications.
• Support and deploy custom RV tools (e.g., Totem, Voltus-XFi) and provide training and documentation to teams.
• Evaluate and adopt improved tool capabilities, automation, and AI/ML approaches to increase analysis accuracy and productivity.

Requirements

Concise list of required and preferred skills and experience for successful performance.

Must-have:

• 6+ years of EMIR and power-integrity experience for silicon design signoff.
• Hands-on experience with EMIR tools such as Redhawk-SC and Voltus (strong Voltus background preferred).
• Experience performing EMIR signoff for complex designs and advanced technology nodes.
• Strong understanding of power integrity fundamentals, electromigration, IR drop analysis, and reliability closure.
• Strong scripting/automation skills (Python, Tcl, Perl, shell, or similar) to build scalable flows.
• Experience integrating EMIR analysis into broader design and signoff flows and working with cross-functional teams.

Nice-to-have:

• Experience with custom RV tools such as Totem and Voltus-XFi.
• Experience defining EMIR signoff criteria with foundries and reliability teams.
• Familiarity with full-chip power analysis, tool correlation, thermal and package interaction, or system-level reliability.
• Experience supporting multiple projects in a centralized methodology/CAD role.
• Interest or experience applying AI/ML to improve analysis efficiency and debug productivity.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (as stated in the posting).

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.