R&D Staff Engineer — LEC and ECO

Job Title

R&D Staff Engineer — LEC and ECO

Role Summary

Senior R&D engineer responsible for design, implementation, and maintenance of core ECO (Engineering Change Order) and LEC-related technologies within Formality. The role involves hands-on development, debugging, and performance optimization of production-grade C++ software used in semiconductor design flows.

The engineer will work on a fast‑paced team focused on producing minimal, correct, and reliable ECO patches, collaborating with R&D peers and customer-facing teams to deliver high-impact solutions.

Experience Level

Senior — expects experienced engineers. Typical guidance in the posting: 5+ years relevant experience with a Bachelor’s degree or 3+ years with a Master’s degree (degree details summarized in Education Requirements).

Responsibilities

Primary responsibilities center on hands-on development, debugging, and technical leadership to improve ECO tool quality, performance, and reliability.

• Design, implement, and deliver core enhancements to Formality ECO technology.
• Maintain, debug, and improve existing functionality to enhance patch quality, tool performance, and memory utilization.
• Lead technical investigations and root-cause analysis for complex production issues and implement robust fixes.
• Collaborate with R&D teams and customer support to translate customer ECO challenges into practical solutions.
• Promote best practices in code quality, testing, and software design to support long-term product health.
• Contribute to advancing ECO verification methodologies and scalable, high-performance solutions for next-generation designs.

Requirements

Must-have technical skills and experience; separate from the formal education requirements listed below.

• Strong software development experience in C++ on UNIX/Linux platforms.
• Proficient in data structures, algorithms, and system design for performance‑critical software.
• Experience working with large, complex commercial codebases and production-grade tools.
• Familiarity with EDA flows and practical ECO workflows.
• Experience with debugging, profiling, and improving tool performance and memory usage.
• Exposure to scripting languages (Python, TCL, Perl, shell) for tooling and automation.
• Familiarity with HDL languages such as Verilog or SystemVerilog, or willingness to learn.
• Effective communication and presentation skills for technical discussions and cross-team collaboration.
• Nice-to-have: knowledge of Logic Equivalence Checking (LEC) and familiarity with modern developer productivity tools (e.g., GitHub Copilot).

Education Requirements

Bachelor’s degree in Electrical, Electronics, or Computer Science Engineering with 5+ years of relevant experience, or a Master’s degree with 3+ years of relevant experience. (The posting implies degree-based requirements; equivalent practical experience may be considered.)

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.