R&D Engineering Staff Engineer

Job Title

R&D Engineering Staff Engineer

Role Summary

Work on system-level functional verification and verification IP for coherent and non-coherent IP designs across high-performance computing, data center, mobile/client, automotive and IoT segments. The role is part of an R&D engineering team responsible for architecting SystemVerilog/UVM testbenches and driving coverage-driven verification closure.

Contribute to reliable, high-performance platform designs by developing and integrating robust verification solutions.

Experience Level

Senior. Typical experience: 10–15 years (B.E./B.Tech route) or 5–9 years (M.E./M.Tech route) in relevant verification or R&D roles.

Responsibilities

Primary responsibilities include functional verification, verification IP development, and collaboration with product teams.

• Design and implement SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IP.
• Create verification plans and drive coverage-driven verification closure on real designs.
• Verify coherent and non-coherent IP designs; develop and maintain verification IPs for complex protocols.
• Debug and resolve issues in verification environments; triage regressions and perform root-cause analysis.
• Collaborate with cross-functional teams and customers to define verification requirements and deliverables.

Requirements

Must-have skills and experience (education specifics are listed under Education Requirements).

• Hands-on experience architecting and building SystemVerilog UVM verification environments and VIP.
• Strong functional verification skills, including coverage-driven methodology and verification planning.
• Protocol experience: UCIe, PCIe, CXL, UniPro, USB, MIPI, HDMI, Ethernet, DDR/LPDDR/HBM or similar high-speed interfaces.
• Scripting and programming: Perl, Python, Shell; familiarity with object-oriented programming concepts.
• Excellent debugging, problem-solving, and analytical skills; experience with checkers/scoreboards and debug flows.
• Effective verbal and written communication and ability to work collaboratively in a team.

Nice-to-have:

• Verification IP development experience across multiple protocols and system-level verification of coherent systems.
• Experience with additional verification tools and automation frameworks beyond SystemVerilog/UVM.

Education Requirements

B.E. / B.Tech in Electrical Engineering or Electronics & Communications Engineering with 10–15 years of relevant experience, OR M.E. / M.Tech in VLSI Design or Microelectronics with 5–9 years of relevant experience. The posting specifies these degree routes with the associated years of experience; no explicit statement about equivalent practical experience or certifications was provided.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.