R&D Engineering Manager

Job Title

R&D Engineering Manager

Role Summary

Lead the physical implementation of PVT Sensor IP across advanced foundry nodes (1.4nm–7nm), owning delivery from floorplanning through GDSII. Manage and grow a team of ASIC physical design engineers, set technical direction, and ensure designs meet performance, power, area (PPA) and schedule targets.

The role requires hands-on technical leadership, cross-functional collaboration with front-end, verification and product teams, and direct customer interaction to resolve delivery and quality issues.

Experience Level

Senior — requires strong leadership and technical delivery experience; posting specifies 10+ years in ASIC or IP physical design.

Responsibilities

Primary responsibilities focus on technical leadership, delivery, and process improvement for PVT Sensor IP physical implementation.

• Lead end-to-end physical implementation of digital modules from floorplan to GDSII across advanced nodes, driving timing closure and power optimization.
• Manage, mentor, and grow a team of physical design engineers; set technical direction and review work.
• Perform hands-on work to unblock critical path analysis, congestion fixes, and sign-off issues when required.
• Collaborate with front-end design, verification, and product engineering to align RTL, constraints, and implementation strategy.
• Plan projects, allocate resources, and manage team budgets across multiple concurrent programs and node bring-ups.
• Interface with customers to gather requirements, provide technical updates, and resolve design issues.
• Drive continuous improvement in design flows and EDA tool usage to improve convergence, PPA, and handoffs to sign-off.

Requirements

Must-have technical and leadership qualifications; one item is listed as a strong plus under preferred.

• 10+ years in ASIC or IP physical design with delivery experience at 7nm or below, including floorplanning, P&R, CTS, and timing closure.
• Deep knowledge of RTL-to-GDSII flow, STA, power analysis, parasitic extraction, and sign-off practices.
• Proven experience managing and mentoring engineering teams and delivering projects on schedule.
• Hands-on experience with Synopsys EDA tools such as IC Compiler II, Fusion Compiler, PrimeTime, and StarRC; ability to optimize tool flows for advanced nodes.
• Experience managing project schedules, resource allocation, and team budgets in multi-program environments.
• Excellent communication skills for technical presentations, cross-functional coordination, and customer-facing updates.
• Nice-to-have: experience with IP quality processes, release workflows, or customer-facing IP delivery.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.