R&D Engineering Director

Job Title

R&D Engineering Director

Role Summary

Lead the Digital Methodology Center of Excellence to define and deploy Design-for-Test (DFT) methodologies and drive adoption of Synopsys TestMAX solutions for complex ASIC and SoC designs. Provide technical leadership for customer engagements, influence product roadmap priorities, and mentor engineering teams to improve test quality and manufacturability.

Experience Level

Senior - requires 15+ years of experience in the semiconductor or EDA industry with a focus on DFT, ATPG, and manufacturing test methodologies.

Responsibilities

Primary responsibilities include methodology strategy, technical leadership, customer deployment, and team mentoring.

• Define and drive corporate and customer-facing DFT methodologies for next-generation ASIC and SoC designs.
• Act as subject matter expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
• Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrappers, IJTAG infrastructures, and embedded test technologies.
• Architect scalable test access and instrumentation networks leveraging IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), and IEEE 1500 standards.
• Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
• Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across multiple programs and business units.
• Collaborate with R&D to influence future product capabilities and roadmap priorities.
• Provide technical leadership for strategic customer engagements, methodology reviews, and complex technical escalations.
• Mentor engineers across teams to develop organizational DFT expertise.

Requirements

Must-have technical skills and domain experience; preferred qualifications listed separately.

• 15+ years of experience in DFT, ATPG, and manufacturing test in the semiconductor or EDA industry.
• Proven experience architecting and implementing DFT solutions for large-scale ASIC and SoC designs.
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
• In-depth knowledge of scan insertion, scan compression, hierarchical DFT methodologies, ATPG, diagnosis, and coverage optimization.
• Familiarity with fault models: stuck-at, transition, path-delay, bridge, and cell-aware.
• Experience developing and deploying JTAG/TAP architectures, boundary scan networks, IJTAG instrumentation networks, and embedded instrument access solutions.
• Expertise integrating DFT IP such as codec/embedded compression, OCC, LBIST, TAP controllers, TDR networks, and IEEE 1500 wrappers.
• Strong understanding of RTL-to-GDSII flows and DFT interactions with synthesis, physical design, timing closure, and signoff.
• Proficiency with scripting for methodology development and automation (Tcl, Python, Perl, Shell).
• Nice-to-have: enterprise-wide DFT standards/signoff experience, advanced-node SoC work, silicon bring-up and yield improvement, functional safety for automotive, industry contributions (publications, patents).

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related field (specified in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.