R&D Engineering Director

Job Title

R&D Engineering Director

Role Summary

Lead an embedded memory design team responsible for architecture, circuit implementation, layout planning, characterization, verification, and model generation for advanced nodes (FinFET). The role combines technical ownership of memory IP quality and delivery with people and project management across Hyderabad and global sites.

Experience Level

Senior — typically 20+ years of hands-on experience in embedded memory design (explicitly stated).

Responsibilities

Accountable for delivery, technical direction, and team development across multiple memory projects.

• Lead a team designing SRAM, register files, TCAM, and ROM architectures and circuits for advanced process nodes.
• Own the full memory design flow: bit cell analysis, architecture, schematic entry, simulation, layout planning, characterization, verification, and model generation.
• Drive low-power and area-efficient circuit design; supervise layout and collaborate with CAD on verification and compiler automation.
• Manage project timelines, prioritize across concurrent projects, and resolve technical and scheduling issues to ensure on-time delivery.
• Interface with characterization, verification, and customer-facing teams to align deliverables and resolve escalations.
• Apply variation-aware design techniques and transistor-level expertise for deep submicron and FinFET technologies.
• Mentor engineers, facilitate technical problem-solving, and foster collaboration across multi-site teams.

Requirements

Must-have technical and leadership qualifications for the role.

• 20+ years of hands-on experience in embedded memory design (SRAM, register file, TCAM, ROM) and circuit implementation.
• Deep expertise across the full memory design flow: architecture, schematic design, layout planning, characterization, timing analysis, and model generation.
• Proven experience leading and managing engineering teams and delivering complex projects on schedule.
• Strong proficiency in transistor-level circuit design for deep submicron and FinFET technologies, including variation-aware techniques.
• Mastery of Perl and Python for design automation and scripting.
• Ability to diagnose silicon/characterization issues, drive root-cause analysis, and resolve customer escalations.
• Nice-to-have: experience with memory compiler development and automation.

Education Requirements

BE/B.Tech/ME/M.Tech/MS in Electrical and Electronics Engineering from a recognized university (specified in source).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.