R&D Engineer, IC Design

Job Title

R&D Engineer, IC Design

Role Summary

Member of the Central Engineering Group memory team responsible for validation of memory compilers and custom memory macros across advanced process nodes (including 2nm). Lead and execute validation activities to ensure correct functionality, timing, power, signal integrity and manufacturability of SRAM, multi-port memories, register files, TCAMs and ROMs.

Experience Level

Senior — typically requires 9+ years of relevant experience.

Responsibilities

Core responsibilities include:

• Lead memory design validation for SRAM, multi-port memories, register files, TCAM, ROM compilers and custom macros in advanced process technologies.
• Perform functional verification, root-cause analysis of design discrepancies, and drive resolutions with design teams.
• Run transistor-level simulations to validate power-up/lock-up behavior and timing/internal margins; identify characterization gaps.
• Perform signal integrity, EM/IR and reliability analysis and assess impact on timing and margins.
• Perform QA and validation checks to ensure accurate timing and power models for memory components.
• Develop automation scripts to streamline verification flows and data analysis.
• Support silicon debug activities and correlate silicon behavior to SPICE models.
• Coordinate validation plans and execution with memory design leads, modeling teams, and managers.

Requirements

Must-have skills and experience:

• Proven experience developing and validating memory macros across multiple architectures.
• Deep understanding of transistor-level circuit behavior and sub-nanometer layout challenges.
• Experience with signal integrity, EM/IR and reliability analysis.
• Hands-on experience with transistor-level simulators and waveform viewers (examples: HSPICE, Spectre, PrimeSim, XARA, nWave).
• Hands-on experience with Cadence schematic/layout editors and related flows.
• Proficient scripting skills for automation (Skill, Perl, Python).
• Experience with Monte Carlo variation analysis and timing characterization methods.
• Knowledge of DFT schemes and chip-level integration.
• Strong debugging, problem-solving, communication and leadership skills.

Nice-to-have:

• Prior experience on bleeding-edge process nodes (e.g., 2nm).

Education Requirements

Master's degree in Electronics Engineering is stated in the posting.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.