R&D Engineer, IC Design 4

Job Title

R&D Engineer, IC Design 4

Role Summary

Responsible for front-end design and verification of ASIC cores, including architecture definition, RTL/logic design, synthesis, and verification using simulation and formal methods. Works with implementation, verification and DFT teams to achieve timing closure for high-frequency designs.

Contribute to high-performance ASIC development in a cross-functional engineering environment.

Experience Level

Senior-level. Typical guidance: Bachelor's degree with 8+ years of relevant experience, or Master's degree with 6+ years.

Responsibilities

Primary duties cover architecture, RTL implementation, synthesis, verification, timing analysis and debugging.

• Define architecture and design logic blocks based on system requirements.
• Implement RTL (Verilog) and perform functional simulation and debugging.
• Develop synthesis constraints and run synthesis flows for design blocks.
• Perform timing analysis using physical implementation data and work toward timing closure.
• Apply formal verification and static checks to ensure correctness.
• Simulate and debug at RTL and gate levels; analyze power and performance impacts.
• Collaborate with implementation, DFT, verification and cross-functional teams to prepare designs for tapeout.

Requirements

Must-have technical skills and experience:

• Proven ASIC front-end design and implementation experience (RTL/Verilog).
• Experience with synthesis tools and flows (Synopsys Design Compiler/DC or Cadence RTL Compiler) and constraint development.
• Timing analysis experience using PrimeTime and knowledge of Liberty (.lib) timing models.
• Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal) and lint tools (Spyglass).
• Scripting proficiency (TCL and/or Perl) for automation and flows.
• Familiarity with DFT/scan methodology and power analysis at RTL and gate level.
• Version control experience (Git, SVN) and collaborative engineering practices.
• Ability to work independently and collaboratively across teams to deliver tapeout-ready designs.

Preferred:

• Experience with both Synopsys and Cadence toolflows for synthesis and formal verification.
• Prior experience on high-frequency designs.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science or a related technical field. The posting specifies a Bachelor's degree with 8+ years of related experience, or a Master's degree with 6+ years; equivalent practical experience is acceptable.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.