R&D Engineer – Frontend Design Flow (Synthesis & Methodology)

Job Title

R&D Engineer – Frontend Design Flow (Synthesis & Methodology)

Role Summary

Develop and maintain frontend synthesis and static timing analysis flows and methodologies to improve design convergence, PPA, and usability of Synopsys logic libraries and tools.

Work within an R&D team that partners with tool engineering, Silicon IP teams, and customer design teams to validate libraries and deliver practical, automated flows.

Experience Level

Mid-level. No explicit years-of-experience specified.

Responsibilities

The role involves running and improving synthesis/STA flows, automating tasks, debugging PPA issues, and validating standard cell libraries in real design contexts.

• Run and ramp up on Synopsys synthesis and STA toolchains (Design Compiler, Fusion Compiler, PrimeTime) to execute frontend flows.
• Develop and optimize frontend design methodologies aligned with standard cell library capabilities and constraints.
• Build and maintain robust synthesis and STA flows to improve design convergence across timing, power, and area.
• Automate repetitive tasks and flow steps using Tcl, Python, or Shell scripting to increase efficiency and reduce manual errors.
• Debug flow issues, analyze synthesis and timing reports, and resolve PPA bottlenecks that block design closure.
• Contribute to QA and validation for new standard cell libraries, ensuring cells perform in real designs.
• Coordinate between tool development, Silicon IP, and customer design teams to align flow improvements with practical needs.

Requirements

Must-have skills are listed first; additional advantageous skills follow.

• Must-have: Strong fundamentals in Digital Electronics and VLSI design.
• Must-have: Solid RTL design skills using Verilog or SystemVerilog.
• Must-have: Proficiency in at least one scripting language (Python, Tcl, Perl, or Shell).
• Must-have: Experience with data analysis, log parsing, or report interpretation to drive flow optimization.
• Nice-to-have: Knowledge of synthesis flows from RTL to gate-level.
• Nice-to-have: Familiarity with static timing analysis, timing constraints (SDC), and PPA optimization.
• Nice-to-have: Practical experience with Synopsys tools such as Design Compiler, Fusion Compiler, and PrimeTime.

Education Requirements

Bachelor's or masters degree in Electronics Engineering, VLSI, Computer Science, or a related technical field (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.